Abstract: A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

Abstract: A semiconductor power network decoupling capacitance (decap) budgeting problem is formulated to minimize the total decap to be added to the network subject to voltage constraints on the network nodes of a semiconductor circuit design. Voltage constraints on the decap to be added are taken into consideration such that the decap can be distributed throughout a hot spot region of the semiconductor circuit design and not be limited to placement at a single location in the circuit. Dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level.

Abstract: Processes and systems (300) for reducing pessimism in cross talk noise aware static timing analysis and thus resulting false path failures use either or both of effective delta delay noise (307) and path based delay noise (311) analysis. Effective delta delay determines an impact (312, 314, 316) on victim timing of an action by aggressors that occur during a region (209, 319, 321) where victim and aggressor timing windows overlap and determines an effective delta delay 317 corresponding to any portion 316 of the impact on victim timing that extends beyond the victim timing window. The effective delta delay is used to adjust the victim timing window. Path based delta delay determines an uncertainty (627, 637) in a switching time corresponding to a particular path for a victim resulting from an action (switching) by aggressors that occurs at the switching time 607, 613, i.e. during a switching time window (a2 to a2+u1) (613, 625) when uncertainty is included.

Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint.

Abstract: A fast transient simulator of SOI MOS circuits uses fast and accurate SOI transistor table models. The simulator uses a representation of a circuit with partitions. Each of partitions is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage, the simulator implements a transformation and uses body charge as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

Abstract: A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.

Abstract: The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.

Abstract: A method for designing and routing circuitry having reduced cross talk. Early noise analysis (22) is performed after global routing (12) but before detailed routing (28) in order to repair problems (24) before detailed routing (28) is performed. In one embodiment, the early noise analysis (22) is preceded by probabilistic extraction (16). In one embodiment, probabilistic extraction (16) includes determining a probability of occurrence for each configuration in a predetermined set of configurations (54). Probabilistic capacitance extraction is then performed (56). A probabilistic distributed coupled RC network is constructed using the extracted capacitances (60). In one embodiment, probabilistic extraction (16) includes estimating aggressor strength (20) using the probabilistic distributed coupled RC network.

Abstract: A fast transient simulator (71) of SOI MOS circuits uses fast and accurate SOI transistor table models (FIGS. 18, 19). The simulator uses a representation of a circuit with partitions (130). Each of partitions (130) is simulated separately for a short time step by numerically solving differential equations describing its transient behavior. Behavior of the whole circuit is simulated in an event driven way where each event corresponds to an integration time step for each partition. Instead of body voltage (Vy), the simulator (71) implements a transformation and uses body charge (Uy) as an independent variable in order to obtain high accuracy and high speed of simulation. Construction of SOI transistor table models (FIGS. 18, 19) results in speed and accuracy enhancements. This transformation allows the reduction of the number of table dimensions exploiting the fact that SOI transistor backgate capacitance is approximately constant.

Abstract: The present invention relates generally methods and apparatus for controlling current demand in an integrated circuit. One embodiment relates to a method that includes detecting if a supply voltage overshoot or a undershoot is present or anticipated, and if detected, controlling current consumed by a power consumption circuitry to ensure that the power supply voltage remains within acceptable levels. Other embodiments relate to an integrated circuit having a capacitive decoupling structure, power consumption circuitry, and power consumption control circuitry for controlling current consumed by at least a portion of the power consumption circuitry. Therefore, embodiments of the invention relate to monitoring and controlling power consumption (i.e. current demand) of a power consumption circuit (such as an integrated circuit) in order to prevent devastating supply voltage undershoots, overshoots, and oscillations.