Abstract: One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions. One general aspect includes a method for modifying a display, the method including: receiving, by a host server, a request for an accessibility component from a web page server. The method also includes receiving, by the host server, a web page component, from the web page server. The method also includes transmitting, by the host server, the accessibility component to the web page server. The method also includes where the accessibility component is configured to modify a web page content based on user input received at the host computer. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.

Abstract: Methods and apparatus to generate addresses in processors are disclosed. An example address generator disclosed herein includes an adder to add a first address component and a second address component to generate an address, a correction indicator to indicate if the address is correct, and a control input to modify an operation of the adder.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. The present invention further relates to satisfying load operations faster than prior art techniques in most cases. Finally, the present invention provides an improved technique for satisfying load operations that does not significantly impact processor performance.

Abstract: A method and apparatus for satisfying load operations by accessing data from a store buffer is described herein. The present invention further relates to satisfying load operations faster than prior art techniques in most cases. Finally, the present invention to provides an improved technique for satisfying load operations that does not significantly impact processor performance.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: A high performance TF-ceramic module for mounting integrated circuit chips thereto and a method of fabricating the module at reduced cost. The substrate includes thin film (TF) layers formed directly on a layered ceramic base. A first thick film wiring layer is formed on or embedded in a top surface of the thick film layered ceramic base using thick film techniques. A first dielectric layer of a polyimide or other organic material, or an insulating material different than the ceramic material is formed on top of the first wiring layer. The dielectric layer may be spun on or sprayed on and baked; vapor deposited; laminated to the ceramic base; or an inorganic layer may be deposited using plasma enhanced chemical vapor deposition (PECVD). Vias are formed through the first dielectric layer. A second wiring layer is formed on the first dielectric layer. A second dielectric layer is formed on the second wiring layer.

Abstract: A method and system in a data processing system for efficiently interfacing with cache memory by allowing a fetcher to read from cache memory while a plurality of data words or instructions are being loaded into the cache. A request is made by a bus interface unit to load a plurality of instructions or data words into a cache. In response to each individual instruction or data word being loaded into the cache by the bus interface unit, there is an indication that the individual one of said plurality of instructions or data words is valid. Once a desired instruction or data word has an indication that it is valid, the fetcher is allowed to complete a fetch operation prior to all of the instructions or data words being loaded into cache. In one embodiment, a group of invalid tag bits may be utilized to indicate to the fetcher that individual ones of a group of instructions or data words are valid in cache after being written into cache by the bus interface unit.

Abstract: When the instruction dispatch unit detects two consecutive immediate instructions in the instruction queue directed to the same execution unit, it dispatches both during the same cycle, making use of both GPR ports for the two required GPR operands. Instruction path directing logic directs the first instruction to the execution decoder of the one execution unit during the first occurring cycle and latches the second instruction until a second occurring cycle. It also directs the first immediate operand of the first instruction to a first input of an execution block in the one execution unit during the first occurring cycle. An operand path directing logic directs the first GPR operand referred to by the first instruction to a second input of the execution block during the first occurring cycle and latches a second GPR operand referred to by the second instruction until the second occurring cycle.

Abstract: A superscalar processor and method for executing fixed-point instructions within a superscalar processor are disclosed. The superscalar processor has a memory and multiple execution units, including a fixed point execution unit (FXU) and a non-fixed point execution unit (non-FXU). According to the present invention, a set of instructions to be executed are fetched from among a number of instructions stored within memory. A determination is then made if n instructions, the maximum number possible, can be dispatched to the multiple execution units during a first processor cycle if fixed point arithmetic and logical instructions are dispatched only to the FXU. If so, n instructions are dispatched to the multiple execution units for execution.

Abstract: A method for speculatively performing store instructions in a parallel processing computer system, the computer system including a completion buffer unit, includes comparing statuses between a first store instruction and at least one second instruction in the completion buffer unit, the at least one second instruction scheduled for completion before the first store instruction, and speculatively completing the first store instruction before the at least one second instruction when the statuses of the first store instruction do not conflict with the at least one second instruction.

Abstract: A method and system are disclosed for managing the deallocation of a rename buffer allocated to an update instruction within a processor. The processor has a number of rename buffers for temporarily storing information associated with instructions executed by the processor, a number of registers, and a memory. According to the present invention, an update instruction is dispatched to the processor for execution. A particular rename buffer is then allocated to the update instruction. An effective address is generated for the update instruction, wherein the effective address specifies an address within the memory to be accessed by the update instruction. Next, the effective address is stored within the particular rename buffer. Prior to completion of the access to the effective address within memory, the effective address is transferred from the particular rename buffer to a particular one of the number of registers.