Patents by Inventor Rajesh Bajaj

Rajesh Bajaj has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Flip chip device having simplified routing
    Patent number: 8362613
    Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: January 29, 2013
    Assignee: STMicroelectronics Pvt Ltd.
    Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
  • FLIP CHIP DEVICE HAVING SIMPLIFIED ROUTING
    Publication number: 20120168934
    Abstract: The present disclosure is directed to a semiconductor die having a chip outline boundary, a die seal, a row of input/output contact pads separated from the chip outline boundary by the die seal, a first row of solder bump connections positioned between the row of input/output contact pads and the die seal, and a second row of solder bump connections separated from the first row of solder bump connections by the row of input/output contact pads.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 5, 2012
    Applicant: STMicroelectronics Pvt Ltd.
    Inventors: Anil Yadav, Sanjeev Kumar Jain, Rajesh Bajaj
  • Phase locked loop (PLL) for integrated circuits
    Patent number: 6888385
    Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree. “This enables the PLL to maintain the proper phase even during a sleep mode of operation.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: May 3, 2005
    Assignee: STMicroelectronics PVT. Ltd.
    Inventors: Rajesh Bajaj, Nipun Padha
  • Phase locked loop (PLL) for integrated circuits
    Publication number: 20040104750
    Abstract: An improved Phase Locked Loop (PLL) for digital integrated circuits. A characteristic of this PLL is that the Voltage Controlled Oscillator (VCO) output is fed to the phase and frequency detector (PFD) input through a clock-tree replica providing a delay equal to the routed clock tree.
    Type: Application
    Filed: August 12, 2003
    Publication date: June 3, 2004
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Rajesh Bajaj, Nipun Padha