Patents by Inventor Rajesh Balachandran

Rajesh Balachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021753
    Abstract: A light-emitting diode (LED) device can include a mesa with a sidewall encompassing a first semiconductor layer, a second semiconductor layer, and an active region between the first semiconductor layer and the second semiconductor layer. The first semiconductor layer and the second semiconductor layer are oppositely doped. The active region includes a quantum well. The LED device can further include at least one epitaxial layer grown over the sidewall of the mesa. The at least one epitaxial layer comprises a semiconductor material having a wider bandgap than a semiconductor material of the quantum well and is configured to induce compressive or tensile strain in the quantum well. The compressive or tensile strain causes a bandgap of a peripheral portion of the quantum well to differ from a bandgap of a central portion of the quantum well, thereby tuning an emission profile (e.g., wavelength and/or intensity) of the LED device.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Alexander TONKIKH, Berthold HAHN, Michael GRUNDMANN, John Joseph CURLEY, Rajesh BALACHANDRAN
  • Publication number: 20230260840
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Application
    Filed: April 24, 2023
    Publication date: August 17, 2023
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
  • Publication number: 20230154856
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of 3-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Patent number: 11637040
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 25, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
  • Patent number: 11594495
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: February 28, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20220310522
    Abstract: A microelectronic device comprises a stack structure comprising insulative levels vertically interleaved with conductive levels. The conductive levels individually comprise a first conductive structure, and a second conductive structure laterally neighboring the first conductive structure, the second conductive structure exhibiting a concentration of ?-phase tungsten varying with a vertical distance from a vertically neighboring insulative level. The microelectronic device further comprises slot structures vertically extending through the stack structure and dividing the stack structure into block structures, and strings of memory cells vertically extending through the stack structure, the first conductive structures between laterally neighboring strings of memory cells, the second conductive structures between the slot structures and strings of memory cells nearest the slot structures. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: March 23, 2021
    Publication date: September 29, 2022
    Inventors: Jordan D. Greenlee, John D. Hopkins, Everett A. McTeer, Yiping Wang, Rajesh Balachandran, Rita J. Klein, Yongjun J. Hu
  • Publication number: 20220208609
    Abstract: A method for mitigating crack propagation during manufacture of semiconductor dies, and associated systems and methods are disclosed herein. The method includes forming holes into a first side of a wafer substrate opposite a second side. The wafer substrate has active components at the second side. Each hole extends from the first side towards the second side an extend to an intermediate depth within the wafer substrate such that a bottom of the holes is spaced vertically apart from the active components on the second side. The holes are configured to inhibit cracks in the wafer substrate from propagating longitudinally across the wafer substrate. The method also includes backgrinding the first side of the wafer substrate to thin the wafer substrate after forming the holes. The method also includes dicing the wafer substrate after backgrinding to separate individual semiconductor dies from each other.
    Type: Application
    Filed: December 29, 2020
    Publication date: June 30, 2022
    Inventors: Wei Yeeng Ng, Rajesh Balachandran, Frank Speetjens, Andrew L. Li, Sukhdeep Kaur, Sangeetha P. Komanduri
  • Patent number: 10075369
    Abstract: Aspects of the present invention include directing traffic in data communications systems. In embodiments of the present invention the traffic is directed based on a Media Access Control (MAC) address table. In embodiments of the present invention traffic directed to an unknown port is blocked to all ports that are in the MAC address table.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: September 11, 2018
    Assignee: DELL PRODUCTS LP
    Inventors: Karthi Kaliyamoorthy, Rajesh Balachandran
  • Publication number: 20160315851
    Abstract: Aspects of the present invention include directing traffic in data communications systems. In embodiments of the present invention the traffic is directed based on a Media Access Control (MAC) address table. In embodiments of the present invention traffic directed to an unknown port is blocked to all ports that are in the MAC address table.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 27, 2016
    Applicant: DELL PRODUCTS L.P.
    Inventors: Karthi Kaliyamoorthy, Rajesh Balachandran