Abstract: A system and method of enhancing the mitigation of side channel attacks on platform interconnects using endpoint HW based detection, synchronization, and re-keying include generating a set of keys for link encryption based on a high entropy seed, storing the set of keys in a deterministic order in a register, detecting that a re-key programmable threshold is met during link encryption with a device, identifying a synchronization point associated with the device, where the synchronization point indicates the device is ready to switch a current key used for link encryption, and synchronizing a rekeying event with the device.

Abstract: Circuitry, systems, and methods are provided for an integrated circuit device including a memory storing a data structure, a cache storing a portion of the structure data, and an acceleration function unit providing hardware acceleration for a host device. The acceleration function unit may provide the hardware acceleration by intercepting a request from the host device to access the memory, where the request comprises an address corresponding to a data node of the data structure, identifying a next data node based at least in part on decoding the data node, and loading the next data node into the cache for access by the host device.

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

Abstract: A receiver includes a first interface to receive content, a second interface to be coupled to a device, and a processor to determine whether the device is a compliant device and to prevent decryption of at least a portion of the content received through the first interface when the device is determined to be a non-compliant device.

Abstract: Methods and apparatus relating to enhancing diagnostic capabilities of computing systems by combining variable patrolling Application Program Interface (API) and comparison mechanism of variables are described. In one embodiment, a first processor core executes a first instance of a workload to generate a first set of safety variables. A second processor core executes a second instance of the workload to generate a second set of safety variables. A third processor core generates a signal in response to comparison of the first set of safety variables and the second set of safety variables. Other embodiments are also disclosed and claimed.

Abstract: An apparatus of a System on Chip (SoC) to implement a one out of two diagnostics (1oo2D) safety system comprises a memory comprising firmware to provide monitoring of the SoC and a second SoC, and a communication interface to provide cross-monitoring between the SoC and the second SoC. The firmware and the communication interface enable the SoC and the second SoC to implement the 1oo2D safety system without significant hardware or software external to the SoC.

Abstract: Systems and methods of delivering data from a range of input devices may involve detecting an availability of data from an input device, wherein the input device is associated with a default input path of a mobile platform. An input device driver can be invoked in a security engine in response to the availability of the data if a hardware component in the default input path is in a secure input mode, wherein the security engine it associated with a secure input path of the mobile platform. Additionally, the input device driver may be used to retrieve the data from the input device into the security engine.

Abstract: Methods and systems may include a computing system having a display, a display controller with a decryption module, and a security element with security logic. The security logic can be configured to establish a secure path between the secure element and the display in response to a secure output mode request, wherein the secure path includes the display controller. In addition, the security logic may be configured to prevent the decryption module from being bypassed, and transmit encrypted data from the secure element to the display via the secure path.

Abstract: Systems and methods of delivering data from a range of input devices may involve detecting an availability of data from an input device, wherein the input device is associated with a default input path of a mobile platform. An input device driver can be invoked in a security engine in response to the availability of the data if a hardware component in the default input path is in a secure input mode, wherein the security engine it associated with a secure input path of the mobile platform. Additionally, the input device driver may be used to retrieve the data from the input device into the security engine.

Abstract: A receiver includes a first interface to receive content, a second interface to be coupled to a device, and a processor to determine whether the device is a compliant device and to prevent decryption of at least a portion of the content received through the first interface when the device is determined to be a non-compliant device.

Abstract: Methods and systems may include a computing system having a display, a display controller with a decryption module, and a security element with security logic. The security logic can be configured to establish a secure path between the secure element and the display in response to a secure output mode request, wherein the secure path includes the display controller. In addition, the security logic may be configured to prevent the decryption module from being bypassed, and transmit encrypted data from the secure element to the display via the secure path.

Abstract: Some embodiments provide determination of a processor performance characteristic associated with a first workload, and determination of a processor performance state for the first workload based on the performance characteristic. Further aspects may include determination of a second processor performance characteristic associated with a second workload, determination of a second processor performance state for the second workload based on the performance characteristic, determination of a similarity between the first performance characteristics and the second performance characteristics, determination of a cluster comprising the first workload and the second workload, and association of a third processor performance state with the cluster, wherein the third processor performance state is identical to the first processor performance state and to the second processor performance state.

Abstract: An electronic device comprises a first processor, a computer readable memory medium and logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which monitors an operating status of one or more critical processes executing on the first processor and implements a recovery process when the one or more of the critical processes executing on the first processor fails. The device further comprises a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state. Other embodiments may be described.

Abstract: Some embodiments involve determination of a first characteristic associated with a first interface displayed by a display, and determination of a second characteristic associated with a second interface displayed by the display. Embodiments may further involve determination of a first power consumption mode for the first interface based at least on the first characteristic, and determination of a second power consumption mode for the second interface based at least on the second characteristic, wherein the first power consumption mode is different from the second power consumption mode.

Abstract: Some embodiments provide determination of a processor performance characteristic associated with a first workload, and determination of a processor performance state for the first workload based on the performance characteristic. Further aspects may include determination of a second processor performance characteristic associated with a second workload, determination of a second processor performance state for the second workload based on the performance characteristic, determination of a similarity between the first performance characteristics and the second performance characteristics, determination of a cluster comprising the first workload and the second workload, and association of a third processor performance state with the cluster, wherein the third processor performance state is identical to the first processor performance state and to the second processor performance state.

Abstract: Some embodiments provide determination of a processor performance characteristic associated with a first workload, and determination of a processor performance state for the first workload based on the performance characteristic. Further aspects may include determination of a second processor performance characteristic associated with a second workload, determination of a second processor performance state for the second workload based on the performance characteristic, determination of a similarity between the first performance characteristics and the second performance characteristics, determination of a cluster comprising the first workload and the second workload, and association of a third processor performance state with the cluster, wherein the third processor performance state is identical to the first processor performance state and to the second processor performance state.

Abstract: Embodiments of methods and apparatus to operate transceiver systems of a wireless platform are generally described herein. Other embodiments may be described and claimed.

Abstract: Techniques for profiling systems, such as mobile or embedded devices, are provided. The techniques can profile code executing on these systems based on power used by that code. The system may profile power usage for the entire system or a subsystem, component, or functional unit thereof, for example. The system may determine when a specified amount of power has been used, and a performance sampler may then temporarily stop execution of the code and sample state data. This sampled state data may be provided to a performance analyzer that determines performance of the executing code.

Abstract: Some embodiments provide determination of a processor performance characteristic associated with a first workload, and determination of a processor performance state for the first workload based on the performance characteristic. Further aspects may include determination of a second processor performance characteristic associated with a second workload, determination of a second processor performance state for the second workload based on the performance characteristic, determination of a similarity between the first performance characteristics and the second performance characteristics, determination of a cluster comprising the first workload and the second workload, and association of a third processor performance state with the cluster, wherein the third processor performance state is identical to the first processor performance state and to the second processor performance state.