Patents by Inventor Rajesh Bansal

Rajesh Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240137729
    Abstract: The present disclosure pertains to a system for delivering location information between a calling party and a called party call including a processor (202), communicatively coupled to a first mobile computing device (106), and a second mobile computing device (110). The first mobile computing device (106), and the second mobile computing device (110) can include a set of sensors configured to determine location of the first mobile computing device (106), and the second mobile computing device (110). The processor (202) can be configured to determine a first displayable location code and a second displayable location code and facilitates transmitting and displaying the first displayable location code to the second mobile computing device (110), and the second displayable location code to the first mobile computing device (106) in online mode. The system (102) can be configured to display the first displayable location code and the second displayable location code in form of audio, text, pop up.
    Type: Application
    Filed: February 22, 2022
    Publication date: April 25, 2024
    Inventors: Kaushal Bansal, Rajesh Kumar
  • Publication number: 20210097449
    Abstract: In one embodiment, a processing device for training a decision tree model includes memory and processing circuitry. The processing circuitry allocates a tree node array in memory, where the number of array elements in the tree node array equals the number of data samples in a training dataset. The processing circuitry also obtains the training dataset, which contains data samples captured at least partially by sensor(s). The processing circuitry then trains the decision tree model. For example, a root node is initially assigned to the data samples in the training dataset. The root node is recursively split into child nodes based on identified branch conditions, where each child node is assigned to a subset of data samples. The tree node array is continuously updated during training to identify the child nodes assigned to the data samples. The processing circuitry then stores the trained decision tree model in memory.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Rita Chattopadhyay, Rajesh Bansal
  • Publication number: 20200311559
    Abstract: In one embodiment, an edge computing device for performing decision tree training and inference includes interface circuitry and processing circuitry. The interface circuitry receives training data and inference data that is captured, at least partially, by sensor(s). The training data corresponds to a plurality of labeled instances of a feature set, and the inference data corresponds to an unlabeled instance of the feature set. The processing circuitry: computes a set of feature value checkpoints that indicate, for each feature of the feature set, a subset of potential feature values to be evaluated for splitting tree nodes of a decision tree model; trains the decision tree model based on the training data and the set of feature value checkpoints; and performs inference using the decision tree model to predict a target variable for the unlabeled instance of the feature set.
    Type: Application
    Filed: June 15, 2020
    Publication date: October 1, 2020
    Inventors: Rita Chattopadhyay, Rajesh Bansal, Yuming Ma, Mrittika Ganguli
  • Patent number: 10161999
    Abstract: Approaches for capturing states of signals of a circuit-under-test are disclosed. A logic analyzer circuit is coupled to the circuit-under-test and is configured to receive a plurality of probe signals and a plurality of trigger signals from the circuit-under-test. The logic analyzer circuit inputs data identifying a subset of the probe signals and a subset of the trigger signals. The logic analyzer circuit selects the subset of trigger signals for input to trigger logic and selects the subset of probe signals in the logic analyzer circuit after the logic analyzer circuit and the circuit-under-test are active. The logic analyzer circuit samples states of the subset of probe signals in response to the trigger logic and stores the sampled states of the subset of probe signals in a memory.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: December 25, 2018
    Assignee: XILINX, INC.
    Inventors: Heera Nand, Niloy Roy, Mahesh Sankroj, Siddharth Rele, Riyas Noorudeen Remla, Rajesh Bansal, Bradley K. Fross
  • Patent number: 9083347
    Abstract: Circuits and methods for capturing internal signal values in a circuit before, during, and after a trigger event are disclosed. For example, a circuit can include a shift register configured to receive data values of an input data set over a plurality of cycles, and a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following the receiving of the trigger signal, where the trigger signal indicates a trigger event. The circuit can also include a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface and the shift register in response to receiving the trigger signal.
    Type: Grant
    Filed: May 16, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Rajesh Bansal
  • Patent number: 8288814
    Abstract: A semiconductor die includes a first set of metal lines and a second set of metal lines. The first set of metal lines and the second set of metal lines are placed in alternate planes and are orthogonal to each other. A via is used to connect a first metal line from the first set of metal lines with a second metal line from the second set of metal lines. The via location is offset such that a side of the first metal line is aligned with a side of the second metal line. Consequently, a metal line adjacent to the first metal line does not need to detour around the via.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: October 16, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Pankaj K Jha, Rajesh Bansal, Chetan Verma
  • Publication number: 20100181683
    Abstract: A semiconductor die includes a first set of metal lines and a second set of metal lines. The first set of metal lines and the second set of metal lines are placed in alternate planes and are orthogonal to each other. A via is used to connect a first metal line from the first set of metal lines with a second metal line from the second set of metal lines. The via location is offset such that a side of the first metal line is aligned with a side of the second metal line. Consequently, a metal line adjacent to the first metal line does not need to detour around the via.
    Type: Application
    Filed: November 17, 2009
    Publication date: July 22, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Pankaj K Jha, Rajesh Bansal, Chetan Verma
  • Publication number: 20060251008
    Abstract: An access-point node to a first network cell of a radio access network, to an access-center node and to a radio access network enable local service providers in rural areas to provide mobile telecommunication at low cost for end users. The access-point node of the invention is configured to establish, maintain, and release a local user-data radio channel, which consists of a first local channel section having as endpoints a first terminal device located in the network cell and the access-point node, and of a second local channel section having as endpoints the access-point node and a second terminal device located in the network cell. The access-point node is configured to exchange packetized user data and control data with an assigned superordinate access-center node for establishing, maintaining and releasing communication between the first terminal device and a third terminal device located outside the network cell. Link cost between the radio access network and the core network may be strongly reduced.
    Type: Application
    Filed: June 30, 2005
    Publication date: November 9, 2006
    Inventors: Michael Wu, Petteri Alinikula, Rajesh Bansal, Mika Skarp, Ram Narayanan