Abstract: The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model.

Abstract: The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.

Abstract: The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.

Abstract: The present invention relates to the use of multiple store buffer forwarding in a microprocessor system with a restrictive memory model. In accordance with an embodiment of the present invention, the system and method allow load operations that are completely covered by two or more store operations to receive data via store buffer forwarding in such a manner as to retain the side effects of the restrictive memory model thereby increasing processor performance without violating the restrictive memory model.

Abstract: The present invention relates to locked memory instructions, and more specifically to a system and method for the high performance execution of locked memory instructions in a system with distributed memory and a restrictive memory model. In accordance with an embodiment of the present invention, a method for executing locked-memory instructions includes decoding a locked-memory instruction, obtaining exclusive ownership of a cacheline to be used by a load-lock operation, setting a bit to indicate the load-lock operation's ownership of the cacheline, and activating a snoop checking process. The method also includes modifying a load data value and storing the modified load data value. The method further includes determining that the cacheline is still exclusively owned, storing the load data value, determining that the cacheline is unsnooped, merging the modified load data value with the load data value, and releasing the locked-memory instruction to be retired.

Abstract: A method and system for reducing power consumption of a non-blocking cache memory within a data processing system is disclosed. In accordance with a method and system of the present disclosure, a detection unit, having several index-matching bits, is associated with the cache memory within the data processing system. A determination is made as to whether or not there is a match in the cache memory, in response to an occurrence of a cache request while the cache memory is performing a linefill operation. In response to a determination that there is not a match for the cache request in the cache memory, another determination is made as to whether or not there is a match for the cache request with a block of information within the ongoing linefill operation.

Abstract: A method and system for reducing bus traffic in a multiple processor system having a shared memory and processor related private caches. Store multiple word instructions are evaluated to determine whether a full cache line is to be modified. If the full cache line is to be stored, a cache line kill is issued on the system bus and the cache line is written to the cache. Any store operation of single word, or multiple words extending over portions of a cache line, invokes conventional memory coherence processes.

Abstract: A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that associates a selected nonphysical address with a corresponding physical address assigned to a device in the data processing system is stored within a first memory of the data processing system. In response to a determination that the first entry set is not stored in the first memory, a determination is made if a second entry set which could contain the particular entry is stored within the first memory. In response to a determination that the second entry set is stored in the first memory, a search of the second entry set is initiated in order to locate the particular entry. In response to locating the particular entry, the selected nonphysical address is translated to the corresponding physical address utilizing the particular entry.

Abstract: First and second store instructions that target one or more locations in a cache memory are identified. A determination is made whether the cache memory is busy. In response to a determination that the cache memory is busy, the operations specified by the first and second store instructions are merged into a single store operation that subsumes store operations specified by the first and second store instructions. Thereafter, the single store operation is performed.

Abstract: A method and system of enhancing memory performance in a data processing system are provided. The data processing system may include a processor having an on-board first-level cache, a second-level cache coupled to the processor, a system bus coupled to the processor, and a main memory coupled to the system bus. When a memory request is received for a cache line at the first-level cache, a determination is made if the memory request is initiated by a store operation. If the memory request results in a hit in the first-level cache and a determination is made that the memory request is store-initiated, a corresponding cache line in a second-level cache is invalidated.

Abstract: A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.

Abstract: In a microprocessor having a plurality of execution units, rename register, architectural registers, and a cache for storing blocks of data, each block having a plurality of words, a method for aligning bytes stored in separate words. In one version, the method includes the steps of reading a first word of data from the cache; rotating the first word to align a first byte with respect to a first byte of a rename register; storing the first aligned byte in the rename register; reading a second word from the cache; rotating the second word to align a second byte with respect to a second byte of the rename register; and storing the second aligned byte in the rename register.

Abstract: A method and system for preventing information corruption in a cache memory due to a bus error which occurs during a cache linefill operation is disclosed. The cache memory includes multiple cache lines, and a tag is associated with each cache line. In accordance with the present disclosure, a tag associated with a cache line is validated before a linefill operation is performed on the cache line. In response to an occurrence of a bus error during the linefill operation, the tag associated with the cache line for which a linefill operation is performed, is invalidated such that the information within the cache line remains valid during a linefill operation unless a bus error occurs.

Abstract: A processor and method of executing instructions within a processor are disclosed, which permit both a branch instruction and a target instruction of the branch instruction to be executed in response to a single instruction fetch. In accordance with an illustrative embodiment, the processor, which has an associated memory, simultaneously fetches a plurality of instructions from the memory. Branch instructions among the plurality of instructions are then detected. In response to a detection of a branch instruction among the plurality of instructions, a determination is made whether a target instruction to be executed in response to execution of the branch instruction is one of the plurality of instructions. In response to a determination that the target instruction is one of the plurality of instructions, the processor executes the target instruction without making an additional instruction fetch.

Abstract: A method for implementing a four-way least recently used cache line replacement scheme in a four-way cache memory is disclosed. The cache memory includes multiple cache lines, and each cache line includes four congruence sets. In accordance with the present disclosure, a 5-bit Least Recently Used (LRU) field is associated with each of the cache lines within the cache memory. For a particular cache line, a set number of a least recently used set among the four congruence sets is stored in any two bits of the LRU field associated with that cache line. Next, a set number of the second least recently used set among the four congruence sets is stored in another two bits of the same LRU field associated with the same cache line. Finally, a last bit of the 5-bit LRU field is set to a specific state in response to a determination of which one of the remaining two sets is the second most recently used set.

Abstract: A method for reducing dispatch stalls includes tracking allocation and deallocation of real rename buffers for instructions dispatched by a dispatch unit, and providing at least one virtual rename buffer for allocation of an instruction when the real rename buffers have been allocated. The method further includes tagging the instruction allocated to the at least one virtual rename buffer with a rename buffer busy signal, wherein the rename buffer busy signal indicates to an execution unit that the instruction cannot be completed. An efficient system for utilization of rename buffers in a superscalar processor includes a plurality of rename buffers, a dispatch unit coupled to the plurality of rename buffers, and an allocation/deallocation table coupled to the dispatch unit and the plurality of rename buffers. Further, the table includes a plurality of real rename buffer slots and at least one virtual rename buffer slot.

Abstract: A microprocessor that dynamically shares cache capacity comprising a controller that determines if all ways for a congruence class of a requested instruction are valid in the instruction cache and if a replacement way for the congruence class of the requested instruction is valid in a data cache. A lookup for the instruction is performed in the cache tags for the instruction cache and the data cache. If a hit occurs in either cache, the instruction is retrieved. If a miss occurs for the instruction in both the instruction cache and the data cache, the controller loads the instruction into either the instruction cache, if the replacement way is valid in the data cache or at least one way for the congruence class of the requested instruction is not valid in the instruction cache, or the data cache, if the replacement way is not valid in the data cache and all ways for the congruence class of the requested instruction are valid in the instruction cache.

Abstract: A data processing system having enhanced memory performance is provided. The data processing system comprises a processor that issues memory requests, a multilevel storage system including a first level cache, a second level cache, and a main memory connected to the processor in a memory hierarchy, and a memory controller. The memory controller retrieves a cache line from main memory, when a memory request for the cache line is received from the processor at the first level cache that causes a miss in both the first level cache and the second level cache. The memory controller loads the retrieved cache line in both the first level cache and the second level cache if the received memory request is a load request, and loads the retrieved cache line in only the first level cache and not the second level cache if the received memory request is a store request.

Abstract: A method and apparatus for executing a single beat write (SBW) store instruction during a cache store linefill operation are disclosed. In accordance with the present disclosure, an address associated with the cache memory store linefill operation is first received. This address comprises a tag portion and an index portion. For the cache store linefill operation, the tag portion of this address is sent to a tag latch while the index portion is sent to a burst index latch. During the cache store linefill operation, a second address associated with the single beat write store instruction is received. This second address also comprises a tag portion and an index portion. In response to a determination that a critical word of the cache memory store linefill has been received, the tag portion of the second address is sent to the tag latch and the index portion of the second address is sent to an SBW index latch.