Abstract: A microprocessor includes a direct access memory (DMA) engine which is responsive to pairs of block indices associated with one or more blocks in a first logical plane and transfers the one or more blocks between the first logical plane, a second logical plane, and a physical memory space according to the pairs of block indices. The logical planes represent two dimensional fields of data such as those found in images and videos. The microprocessor further comprises cache memory which updates its content with one or more cache-blocks which are in the neighborhood of the one or more blocks improving the operation of the cache memory by increasing cache hits. The DMA engine may further operate on n-dimensional blocks in a n-dimensional logical space. The microprocessor further includes special-purpose instructions, operative on a single-instruction-multiple-data (SIMD) computation unit, especially tailored to perform matrix operations.

Abstract: A low latency, high throughput communication system applicable to real-time communications, such as real-time audio and video, controls the total in-transit data between a transmitting application and a receiving application to a target amount using feedback. As a result, the system operates at about the same throughput as it does when modem and other buffers associated with the system are always full, but at a substantially lower latency and with the modem and other buffers less than full. The system is applicable to both modem-to-modem telephone communications and internet communications in accordance with the TCP and UDP protocols. The system includes a forward error correction and retransmission scheme for use with the UDP protocol, and also includes a scheduling protocol for use in association with virtual channels.