Patents by Inventor Rajesh D. Rajavel
Rajesh D. Rajavel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9064992Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.Type: GrantFiled: August 14, 2014Date of Patent: June 23, 2015Assignee: HRL Laboratories, LLCInventors: Brett Z Nosho, Rajesh D Rajavel, Hasan Sharifi, Sevag Terterian
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Patent number: 8969986Abstract: An infrared photo-detector with multiple discrete regions of a first absorber material. These regions may have geometric shapes with sloped sidewalls. The detector also may include a second absorber region comprising a second absorber material that absorbs light of a shorter wavelength than the light absorbed by the multiple discrete absorber regions of the first absorber material. The geometric shapes may extend only through the first absorber material. Alternatively, the geometric shapes may extend partially into the second absorber region. The detector has a metal reflector coupled to the multiple discrete absorber regions. The detector also has a substrate containing the discrete absorber regions and the second absorber region. The substrate can further include geometric shaped features etched into the substrate, with those features formed on the side of the substrate opposite the side containing the discrete absorber regions and the second absorber region.Type: GrantFiled: February 28, 2011Date of Patent: March 3, 2015Assignee: HRL Laboratories, LLCInventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Hasan Sharifi
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Patent number: 8946839Abstract: An absorber is disclosed. The disclosed absorber contains a base layer, and a plurality of pillars disposed above the base layer and composed of material configured to absorb an incident light and generate minority electrical carriers and majority electrical carrier, wherein the height of the pillars is predetermined to provide a common pyramidal outline shared by the pillars in the plurality of pillars.Type: GrantFiled: August 20, 2009Date of Patent: February 3, 2015Assignee: HRL Laboratories, LLCInventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, James H. Schaffner
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Publication number: 20150014537Abstract: A dual-band infrared detector is provided. The dual-band infrared detector includes a first absorption layer, a barrier layer coupled to the first absorption layer, and a second absorption layer coupled to the barrier layer. The first absorption layer is sensitive to only a first infrared wavelength band and the second absorption layer is sensitive to only a second infrared wavelength band that is different from the first infrared wavelength band. The dual-band infrared detector is capable of detecting the first wavelength band and the second wavelength band by applying a first bias voltage of a first polarity to the first absorption layer and by applying a second bias voltage of a second polarity that is opposite the first polarity to the second absorption layer, wherein the first bias voltage and the second bias voltage each have a magnitude of less than about 500 mV.Type: ApplicationFiled: July 15, 2013Publication date: January 15, 2015Inventors: Rajesh D. Rajavel, Terence J. deLyon
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Patent number: 8900896Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.Type: GrantFiled: February 17, 2011Date of Patent: December 2, 2014Assignee: HRL Laboratories, LLCInventors: Yakov Royter, Rajesh D. Rajavel, Irina Ionova, Sophi Ionova
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Patent number: 8847202Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.Type: GrantFiled: January 17, 2012Date of Patent: September 30, 2014Assignee: HRL Laboratories, LLCInventors: Brett Z. Nosho, Rajesh D. Rajavel, Hasan Sharifi, Sevag Terterian
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Patent number: 8835979Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.Type: GrantFiled: June 3, 2011Date of Patent: September 16, 2014Assignee: HRL Laboratories, LLCInventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
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Patent number: 8692295Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.Type: GrantFiled: September 25, 2009Date of Patent: April 8, 2014Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Stephen Thomas, III
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Patent number: 8093559Abstract: The present invention provides a two-terminal infrared detector capable of detecting a plurality of bands, such as three bands, over the visible and short-wave infrared bands. Detection of three colors enables one to construct composite imagery that provide significantly added contract in comparison to typical grayscale images. In some variations, the device includes multiple absorber and barrier layers that consist of distinct engineered semiconductor alloys which are closely lattice matched to InP.Type: GrantFiled: December 2, 2008Date of Patent: January 10, 2012Assignee: HRL Laboratories, LLCInventor: Rajesh D. Rajavel
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Patent number: 7932512Abstract: Fabrication of a photonic integrated circuit (PIC) including active elements such as a semiconductor optical amplifier (SOA) and passive elements such as a floating rib waveguide. Selective area doping through ion implantation or thermal diffusion before semiconductor epitaxial growth is used in order to define the contact and lateral current transport layers for each active device, while leaving areas corresponding to the passive devices undoped. InP wafers are used as the substrate which may be selectively doped with silicon.Type: GrantFiled: September 27, 2006Date of Patent: April 26, 2011Assignee: HRL Laboratories, LLCInventors: Yakov I. Royter, Rajesh D. Rajavel, Stanislav I. Ionov, Irina Ionova, legal representative, Sophi Ionova, legal representative
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Patent number: 7928389Abstract: An apparatus and method for a detector are disclosed. The apparatus disclosed contains an extractor layer, an absorber layer disposed adjacent to the extractor layer, a first electrical contact and a second electrical contact. The absorber layer is configured to absorb photons of incident light and generate minority electrical carriers and majority electrical carriers. In the disclosed apparatus, the top surface of the absorber layer is shaped as a pyramid, the extractor layer is electrically connected with the absorber layer and with the first electrical contact for extracting the minority electrical carriers, and the absorber layer is electrically connected with the extractor layer and with the second electrical contact to extract the majority electrical carriers.Type: GrantFiled: August 20, 2009Date of Patent: April 19, 2011Assignee: HRL Laboratories, LLCInventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Joseph S. Colburn
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Patent number: 7800067Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.Type: GrantFiled: December 1, 2009Date of Patent: September 21, 2010Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
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Patent number: 7755023Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.Type: GrantFiled: October 9, 2007Date of Patent: July 13, 2010Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
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Patent number: 7692212Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.Type: GrantFiled: December 7, 2004Date of Patent: April 6, 2010Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Stephen Thomas, III
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Patent number: 7652252Abstract: Electronically tunable and reconfigurable hyperspectral IR detectors and methods for making the same are presented. In one embodiment, a reconfigurable hyperspectral sensor (or detector) detects radiation from about 0.4 ?m to about 2 ?m and beyond. This sensor is configured to be compact, and lightweight and offers hyperspectral imaging capability while providing wavelength agility and tunability at the chip-level. That is, the sensor is used to rapidly image across diverse terrain to identify man-made objects and other anomalies in cluttered environments.Type: GrantFiled: October 8, 2007Date of Patent: January 26, 2010Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Andrew T. Hunter
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Patent number: 7582536Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.Type: GrantFiled: August 14, 2008Date of Patent: September 1, 2009Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Mary Y. Chen, Steven S. Bui, David H. Chow, James Chingwei Li, Mehran Mokhtari, Marko Sokolich
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Patent number: 7569872Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.Type: GrantFiled: December 20, 2005Date of Patent: August 4, 2009Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter
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Patent number: 7531851Abstract: An electronic device contains a substrate, a sub-collector supported by the substrate, an un-doped layer having a selectively implanted buried sub-collector and supported by the sub-collector, an As-based nucleation layer partially supported by the un-doped layer, a collector layer supported by the As-based nucleation layer, a base layer supported by the collector layer, an emitter layer and a base contact supported by the base layer, an emitter cap layer supported by the emitter layer, an emitter contact supported by the emitter cap layer, and a collector contact supported by the sub-collector. A method provides for selecting a first InP layer, forming an As-based nucleation layer on the first InP layer, and epitaxially growing a second InP layer on the As-based nucleation layer.Type: GrantFiled: February 28, 2007Date of Patent: May 12, 2009Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Mary Y. Chen, Steven S. Bui, David H. Chow, James Chingwei Li, Mehran Mokhtari, Marko Sokolich
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Patent number: 7372084Abstract: Low power double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.Type: GrantFiled: December 20, 2005Date of Patent: May 13, 2008Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, Kenneth Elliott, David H. Chow
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Patent number: 7368765Abstract: Bipolar junction transistors (BJTs) and single or double heterojunction bipolar transistors with low parasitics, and methods for making the same is presented. A transistor is fabricated such that the collector region underneath a base contact area is deactivated. This results in a drastic reduction of the base-collector parasitic capacitance, Cbc. An embodiment of the present invention provides a transistor architecture for which the base contact area can be decoupled from the collector and hence allows for dramatic reduction in the parasitics of transistors.Type: GrantFiled: December 20, 2005Date of Patent: May 6, 2008Assignee: HRL Laboratories, LLCInventors: Rajesh D. Rajavel, David H. Chow, Tahir Hussain, Yakov Royter