Patents by Inventor Rajesh G. Shakkarwar

Rajesh G. Shakkarwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7392398
    Abstract: A method and apparatus for protection of computer assets from unauthorized access is described. A protection engine is incorporated into microprocessor support circuitry to control access to computer assets, for example, BIOS memory and peripheral devices. The protection engine is capable of monitoring the state of an switch and controlling access to computer assets based, in part, on the state of the switch. The protection engine is capable of authenticating the source of interface control commands using cryptographic techniques. The protection engine provides protection against computer viruses, malicious cookies and java/javascript applets, macros, unauthorized remote access to a computer system, and other forms of unauthorized access.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: June 24, 2008
    Assignee: ATI International SRL
    Inventor: Rajesh G. Shakkarwar
  • Publication number: 20080120717
    Abstract: The present invention generally relates to a computer security system for use in the identification and authentication of a user prior to an on-line transaction. In one aspect, a method for enrolling a user in a system configured to identify and authenticate the user is provided. The method includes collecting a username and password to identify the user. The method further includes extracting device data from a user machine to uniquely identify the machine. The method also includes generating a user profile based upon the device data and the username and password. Additionally, the method includes transmitting the user profile to a server machine to be stored. In another aspect, a computer-readable medium including a set of instructions that when executed by a processor cause the processor to enroll a user in a system configured to identify and authenticate the user is the provided. In yet a further aspect, a system for identifying and authenticating a user is provided.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventor: Rajesh G. Shakkarwar
  • Publication number: 20080120507
    Abstract: The present invention generally relates to a computer security system for use in the authentication of a user prior to setting up an on-line account. In one aspect, a method for authenticating a user in a system configured to identify and authenticate the user is provided. The method includes prompting the user to answer at least one initial question. The method further includes obtaining data about the user from a data source based on the answer to the at least one initial question. The method also includes reviewing the data from the data source and generating at least one specific personal question based on the data from the data source. Additionally, the method includes prompting the user to answer the at least one specific personal question and verifying the answer to the at least one specific personal question.
    Type: Application
    Filed: January 30, 2007
    Publication date: May 22, 2008
    Inventor: Rajesh G. Shakkarwar
  • Publication number: 20080120229
    Abstract: The present invention generally relates to a system and a method for establishing a separate session during an on-line session. In one aspect, a method for establishing a session with a server during an on-line transaction session is provided. The method includes detecting an on-line payment page and inserting a code into the on-line payment page, wherein the code is scripted to open a first pop-up window. The method further includes prompting a user via the first pop-up to answer a question, wherein the question is used to determine if a secure payment process is to be used. Additionally, the method includes opening the session with the server via a second pop-up window if the answer to the question is affirmative.
    Type: Application
    Filed: November 21, 2007
    Publication date: May 22, 2008
    Inventors: Sanjaykumar Hanmantrao Patil, Rajesh G. Shakkarwar
  • Publication number: 20080120195
    Abstract: The present invention generally relates to a computer security system for use in the identification and authentication of a user prior to an on-line transaction. In one aspect, a method for facilitating a secure transaction over a network is provided. The method includes collecting a username and password associated with a user of the machine. The method further includes verifying that the username and password matches a previously collected username and password in an identity profile. The method also includes collecting device data from a user machine to uniquely identify the machine. Additionally, the method includes verifying that the device data matches previously collected device data in the identity profile. In another aspect, a computer-readable medium including a set of instructions that when executed by a processor cause the processor to facilitate a secure transaction over a network is provided. In yet a further aspect, a system for facilitating a secure transaction is provided.
    Type: Application
    Filed: November 21, 2006
    Publication date: May 22, 2008
    Inventor: Rajesh G. Shakkarwar
  • Publication number: 20040215986
    Abstract: Systems and methods for dynamic power management of electronic devices are disclosed. In one form, a system employing dynamic power management for electronic devices includes a central processing unit operable to process information via a communication bus. The system includes a clock generator and a voltage generator coupled to the processing unit and operably associated with the communication bus having multiple operating voltage levels. The clock generator and communication bus are operated at variable clock rates and voltage levels to ensure bandwidth requirements are satisfied for communicating and processing information. In this manner, power consumption of the system may be dynamically managed while providing sufficient bandwidth for the system.
    Type: Application
    Filed: April 25, 2003
    Publication date: October 28, 2004
    Inventor: Rajesh G. Shakkarwar
  • Patent number: 6694492
    Abstract: A method and apparatus for optimizing production yield and operational performance of integrated circuits is provided. A nominal operating voltage is used to categorize integrated circuits into a plurality of performance categories, and the nominal operating voltage is adjusted for each performance category to optimize the yield within that performance category. Integrated circuits may be operated at different operating rates according to their performance categories. The operating rates of an integrated circuit may be controlled by programming a clock register for the integrated circuit. Correct programming of the clock register may be assured by programming a one-time-programmable device. A one-time-programmable device may also be used to program the nominal operating voltage once the optimal nominal operating voltage has been determined. A diagnostic program may be used to select optimum performance parameters for an integrated circuit.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: February 17, 2004
    Assignee: ATI International SRL
    Inventor: Rajesh G. Shakkarwar
  • Patent number: 6154419
    Abstract: A method and apparatus for providing compatibility with synchronous dynamic random access memory (SDRAM) and double data rate (DDR) memory is provided. While memory accessing agents, such a microprocessors, typically have a fixed memory access size (e.g., number of bits or bytes exchanged with a memory device in a single operation), DDR memory provides twice the memory burst capability of SDRAM. A method and apparatus is provided to allow memory access agents to exchange data with both SDRAM and DDR memory. Smaller groups of data may be combined or larger groups of data may be separated to allow compatibility. Buffering is provided to accommodate proper timing. Both SDRAM and DDR memory may be used simultaneously.
    Type: Grant
    Filed: March 13, 2000
    Date of Patent: November 28, 2000
    Assignee: ATI Technologies, Inc.
    Inventor: Rajesh G. Shakkarwar
  • Patent number: 5933611
    Abstract: Method and apparatus for improving bus utilization on a bus having a tiered topology, by estimating the worst-case transaction duration time for executing a transaction. The sum of three delays D.sub.fixed, D.sub.data and D.sub.hub.sbsb.--.sub.depth, is detemined, where D.sub.fixed is a delay component which can depend on the transmission duration type of the transaction, as well as other fixed delays; D.sub.data is a delay component which depends on a number N.sub.bytes of bytes to be transmitted for the transaction, and D.sub.hub.sbsb.--.sub.depth is a delay component which depends (in one aspect) on the actual maximum hub depth in the bus topology, or which depends (in another aspect) on the actual hub depth of the target device.
    Type: Grant
    Filed: June 23, 1997
    Date of Patent: August 3, 1999
    Assignee: Opti Inc.
    Inventor: Rajesh G. Shakkarwar