Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: A receiver includes a main loop (222) having a main VCO (210) and a secondary loop (224) having a secondary VCO (216). The receiver momentarily phase locks an incoming RF signal (228), and then samples and stores a correction voltage (240) being applied to the main VCO (210). The main loop (222) is then put into a non-phase locked mode of operation and the stored correction voltage is applied through a receive automatic tuning circuit (218) to the main VCO (210) for the duration of the incoming RF signal (228). This effectively calibrates the LO frequency (230) of the receiver to the incoming RF signal frequency (228).

Abstract: A SONAD (110) control system (100) detects a received signal strength (RSSI) for a radio frequency (RF) signal (102), selects a threshold transfer function (400-404) in response thereto, generates a threshold control signal in response to the transfer function, and utilizes the threshold control signal to select the SONAD threshold value. During operation, the control system (100) decreases the attenuation of background noise levels for weak RF signals.

Abstract: A radio receiver operates primarily in a first operating mode to process received signals (410). When a carrier signal detect is triggered while in the first operating mode (415, 420), the receiver temporarily operates in a second operating mode which has receiver parameters selected to reduce carrier detect falsing when compared to the first operating mode (430). Preferably, in the second operating mode, the receiver's frequency and time response characteristics are modified to facilitate carrier squelch detection. Carrier squelch is performed if a carrier signal detect is triggered while the receiver operates in the second operating mode (440, 450, 460, 470).

Abstract: A single-chip transceiver integrated circuit (100) has multiple on-chip circuits that implement receiver functions, transmitter functions, and audio processing functions. The IC (100) has interfaces (220, 240, 252, 270, 260, 245, 288, 290) which are situated among the on-chip circuits, and which couple one on-chip circuit to another. At least some of these on-chip interfaces (220, 240, 245, 252, 270) are configurable to couple an off-chip processing circuit to substitute for a corresponding on-chip circuit. In the preferred embodiment, the single-chip transceiver IC (100) supports radio configurations having off-chip versions of corresponding on-chip circuits for performing receiver front-end functions, synthesizer functions, reference oscillator functions, and audio processing functions.

Abstract: A detector circuit (100) for detecting signaling information transmitted with a radio frequency (RF) signal for interpretation by a radio receiver includes a first low pass filter (105) for filtering demodulated audio signals that are directly coupled thereto and for providing a first filtered signal. A second low pass filter (109) is directly coupled with the first low pass filter (105) for filtering the first filtered signal and providing a second filtered signal. A signaling detector (111) is then directly coupled with the second low pass filter (109) for determining the frequency and/or bit code of signaling information included in the second filtered signal.

Abstract: A sampled data filter (400) provides on-chip blocking of DC signals. The addition of a very long time constant (VLTC) integrator (412) into the negative feedback path (414) of a first sampled data integrator (402) provides a lower corner frequency (502) with a zero at DC. The lower corner frequency (502) is adjustable while the desired frequency response is maintained.