Abstract: Test structures for wafers are disclosed. A device may include a silicon wafer including a number of die and a scribe area between two die of the number of die. The scribe area may include one or more test structures. The test structures may include a p-doped region and an n-doped region adjacent to the p-doped region. The test structures may also include a first contact electrically coupled to the p-doped region and a second contact electrically coupled to the n-doped region. The second contact may be proximate to the first contact. Associated devices, systems, and methods are also disclosed.

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

Abstract: Methods, systems, and devices for leakage source detection are described. In some cases, a testing device may scan a first set of access lines of a memory die that have a first length and a second set of access lines of the memory die that have a second length different than the first length. The testing device may determine a first error rate associated with the first set of access lines and a second error rate associated with the second set of access lines. The testing device may categorize a performance of the memory die based on the first and second error rates. In some cases, the testing device may determine a third error rate associated with a type of error based on the first and second error rates and may categorize the performance of the memory die based on the third error rate.

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Abstract: Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.

Abstract: Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.

Abstract: Some embodiments include methods for quality testing material removal procedures. A test structure is formed to contain a pair of electrically conductive segments. The segments are the same relative to a detectable property as long as they are electrically connected, but becoming different relative to such property if they are disconnected from one another. A material is formed over the test structure, and across a region of a semiconductor substrate proximate to the test structure. The material is subjected to a procedure which removes at least some of it, and which fabricates a structure of an integrated circuit construction in the region proximate to the test structure. After the procedure, it is determined if the segments are the same relative to the detectable property.