Patents by Inventor Rajesh Kaushik
Rajesh Kaushik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7613853Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.Type: GrantFiled: October 25, 2004Date of Patent: November 3, 2009Assignee: STMicroelectronics Pvt. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Patent number: 7218147Abstract: An improved input buffer providing configurable single-ended and differential signaling capability, comprising an input signal comparator, a first pad connected to one input of the comparator. An internal reference voltage source may be connected to one terminal of a first selection switch. The second terminal of the first selection switch is connected to the second input of the comparator and one terminal of a second selection switch is connected to the second input of the comparator. Further, a second input pad is connected to the second terminal of the second selection switch. The invention also includes a mode selector that enables the first selection switch and disables the second selection switch for providing single-ended operation using the internal reference voltage source, or enables the second selection switch and disables the first selection switch for enabling differential operation or single-ended operation using an external voltage reference.Type: GrantFiled: October 1, 2004Date of Patent: May 15, 2007Assignee: STMicroelectronics PVT. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Patent number: 7157936Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.Type: GrantFiled: January 17, 2003Date of Patent: January 2, 2007Assignee: STMicroelectronics Pvt. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Patent number: 7154318Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresisType: GrantFiled: November 18, 2004Date of Patent: December 26, 2006Assignee: STMicroelectronics PVT. Ltd.Inventors: Manoj Kumar Sharma, Rajesh Kaushik
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Publication number: 20050174146Abstract: An improved input buffer providing configurable single-ended and differential signaling capability, comprising an input signal comparator, a first pad connected to one input of the comparator. An internal reference voltage source may be connected to one terminal of a first selection switch. The second terminal of the first selection switch is connected to the second input of the comparator and one terminal of a second selection switch is connected to the second input of the comparator. Further, a second input pad is connected to the second terminal of the second selection switch. The invention also includes a mode selector that enables the first selection switch and disables the second selection switch for providing single-ended operation using the internal reference voltage source, or enables the second selection switch and disables the first selection switch for enabling differential operation or single-ended operation using an external voltage reference.Type: ApplicationFiled: October 1, 2004Publication date: August 11, 2005Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Publication number: 20050146367Abstract: An improved output buffer having single ended as well as differential signaling capabilities, providing symmetrical outputs for differential output configurations for both synchronous and asynchronous applications, comprising: a pair of flip-flops receiving complementary input signals, a pair of transmitters each having its input connected to the output of one of the flip-flops and providing its output to an output pin, a sense block that senses the transition on complementary input signals and generates a pulse at each transition, and a multiplexer having its output connected to the clock input of said pair of flip flop and one input connected to the output of the sense block for asynchronous mode operation, the second input connected to a clock signal for synchronous mode operation and a select input that enables either asynchronous mode or synchronous mode operation.Type: ApplicationFiled: October 25, 2004Publication date: July 7, 2005Inventors: Rajat Chauhan, Rajesh Kaushik
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Publication number: 20050127970Abstract: An Input Output Block (IOB) provides programmable hysteresis to support multiple IO standards including a differential amplifier having one input coupled to an input signal and its second input coupled to a complementary input signal in the case of differential signalling, or to a reference voltage for the case of single-ended signalling, a pair of series coupled digital inverters coupled to one output of said differential amplifier, one or more transistors coupled in parallel with each input transistor of the differential amplifier, each transistor of each parallel coupled set being of a different size relative to the corresponding input transistor, the control terminal of each parallel coupled transistor in each set being coupled to the output of one of said series coupled inverters such that positive feedback is provided directly or indirectly through a selection switch, and hysteresis control bits that symmetrically enable or disable each said selection switch to provide a programmable level of hysteresisType: ApplicationFiled: November 18, 2004Publication date: June 16, 2005Inventors: Manoj Sharma, Rajesh Kaushik
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Patent number: 6856179Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.Type: GrantFiled: September 12, 2003Date of Patent: February 15, 2005Assignee: STMicroelectronics Pvt. Ltd.Inventors: Rajesh Kaushik, Rajesh Narwal
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Publication number: 20040108875Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.Type: ApplicationFiled: September 12, 2003Publication date: June 10, 2004Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rajesh Kaushik, Rajesh Narwal
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Publication number: 20030172363Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.Type: ApplicationFiled: January 17, 2003Publication date: September 11, 2003Applicant: STMicroelectronics Pvt. Ltd.Inventors: Rajat Chauhan, Rajesh Kaushik
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Publication number: 20030020531Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.Type: ApplicationFiled: July 26, 2002Publication date: January 30, 2003Applicant: STMicroelectronics Ltd.Inventor: Rajesh Kaushik