Patents by Inventor Rajesh Kota

Rajesh Kota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10042804
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: August 7, 2018
    Assignee: Sanmina Corporation
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20150074325
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: November 3, 2014
    Publication date: March 12, 2015
    Applicant: MEMORY INTEGRITY, LLC
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 8930636
    Abstract: One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: January 6, 2015
    Assignee: NVIDIA Corporation
    Inventors: Joel James McCormack, Rajesh Kota, Olivier Giroux, Emmett M. Kilgariff
  • Patent number: 8898254
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: November 25, 2014
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20140025891
    Abstract: One embodiment sets forth a technique for ensuring relaxed coherency between different caches. Two different execution units may be configured to access different caches that may store one or more cache lines corresponding to the same memory address. During time periods between memory barrier instructions relaxed coherency is maintained between the different caches. More specifically, writes to a cache line in a first cache that corresponds to a particular memory address are not necessarily propagated to a cache line in a second cache before the second cache receives a read or write request that also corresponds to the particular memory address. Therefore, the first cache and the second are not necessarily coherent during time periods of relaxed coherency. Execution of a memory barrier instruction ensures that the different caches will be coherent before a new period of relaxed coherency begins.
    Type: Application
    Filed: July 20, 2012
    Publication date: January 23, 2014
    Inventors: Joel James MCCORMACK, Rajesh KOTA, Olivier GIROUX, Emmett M. KILGARIFF
  • Publication number: 20140013079
    Abstract: A multi-processor computer system is described in which transaction processing is distributed among multiple protocol engines. The system includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: Memory Integrity, LLC
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 8572206
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: October 29, 2013
    Assignee: Memory Integrity, LLC
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Patent number: 8185602
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: May 22, 2012
    Assignee: Newisys, Inc.
    Inventors: Charles Edward Watson, Jr., Rajesh Kota, David Brian Glasco
  • Publication number: 20120089787
    Abstract: A multi-processor computer system is described in which transaction processing in each cluster of processors is distributed among multiple protocol engines. Each cluster includes a plurality of local nodes and an interconnection controller interconnected by a local point-to-point architecture. The interconnection controller in each cluster comprises a plurality of protocol engines for processing transactions. Transactions are distributed among the protocol engines using destination information associated with the transactions.
    Type: Application
    Filed: December 15, 2011
    Publication date: April 12, 2012
    Inventors: Charles Edward Watson, JR., Rajesh Kota, David Brian Glasco
  • Patent number: 7577727
    Abstract: According to the present invention, methods and apparatus are provided to allow dynamic multiple cluster system configuration changes. In one example, processors in the multiple cluster system share a virtual address space. Mechanisms for dynamically introducing and removing processors, I/O resources, and clusters are provided. The mechanisms can be implemented during reset or while a system is operating. Links can be dynamically enabled or disabled.
    Type: Grant
    Filed: June 27, 2003
    Date of Patent: August 18, 2009
    Assignee: Newisys, Inc.
    Inventors: Rajesh Kota, Shashank Newawarker, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7577755
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished without the use of a dedicated wire.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 18, 2009
    Assignee: Newisys, Inc.
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Patent number: 7418517
    Abstract: Methods and apparatus are provided for improving the distribution of system management signals within a computer system complex. Mechanisms are provided for transmission both within a box and between computer system boxes. Local routing tables and general routing tables allow the distribution of system management signals precisely to resources associated with particular partitions. Signals are sequenced to put resources associated with one or more boxes in the appropriate states. The distribution of signals between boxes in the computer system complex can be accomplished with the use of a dedicated wire.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 26, 2008
    Assignee: Newisys, Inc.
    Inventors: Carl Zeitler, David Brian Glasco, Les Record, Richard R. Oehler, William G. Kulpa, Guru Prasadh, Rajesh Kota
  • Patent number: 7395347
    Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: July 1, 2008
    Assignee: Newisys, Inc,
    Inventors: Shashank Nemawarkar, Rajesh Kota, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7386626
    Abstract: Improved techniques are provided for reducing latency in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be encapsulated as inter-cluster packets and stored in a transmission buffer pending transmission on an inter-cluster link. When the transmission buffer is empty, a control character is transmitted on an inter-cluster link. The control character is not stored in the transmission buffer or in a reception buffer, but instead is dropped. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links, including the symbol(s) of the control character.
    Type: Grant
    Filed: June 23, 2003
    Date of Patent: June 10, 2008
    Assignee: Newisys, Inc.
    Inventors: Rajesh Kota, Shashank Nemawarkar, Guru Prasadh, Carl Zeitler, David B. Glasco
  • Patent number: 7366879
    Abstract: A method and apparatus are provided for entering and exiting multiple threads within a multithreaded processor. A state machine is maintained to indicate a respective status of an associated thread of multiple threads being executed within a multithreaded processor. A change of status for a first thread within the multithreaded processor is detected and, responsive to the change of status for the first thread within the multithreaded processor, a partitioning scheme for the functional unit is altered to service a second thread, but not the first thread, within the multithreaded processor when the change of the status of the first thread comprises a transition from an active state to an inactive state.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: April 29, 2008
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu
  • Patent number: 7353370
    Abstract: A system includes a multithreaded processor, a memory to store the plurality of threads, and a bus to deliver the plurality of threads to the multithreaded processor. The multithreaded processor includes an event detector to detect a first event indication for a first thread. The event detector, responsive to the detection of the first event indication for the first thread, monitors a second thread being processed within the multithreaded processor to detect a clearing point for the second thread and, responsive to the detection of the clearing point for the second thread clears a functional unit within the multithreaded processor for at least the first thread.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: April 1, 2008
    Assignee: Intel Corporation
    Inventors: Dion Rodgers, Darrell Boggs, Amit Merchant, Rajesh Kota, Rachel Hsu, Keshavan Tiruvallur
  • Patent number: 7296121
    Abstract: A computer system having a plurality of processing nodes interconnected by a first point-to-point architecture is described. Each processing node has a cache memory associated therewith. A probe filtering unit is operable to receive probes corresponding to memory lines from the processing nodes and to transmit the probes only to selected ones of the processing nodes with reference to probe filtering information. The probe filtering information is representative of states associated with selected ones of the cache memories.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: November 13, 2007
    Assignee: Newisys, Inc.
    Inventors: Eric Morton, Rajesh Kota, Adnan Khaleel, David B. Glasco
  • Patent number: 7281055
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: October 9, 2007
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 7251698
    Abstract: A multi-processor computer system is described in which address mapping, routing, and transaction identification mechanisms are provided which enable the interconnection of a plurality of multi-processor clusters, wherein the number of processors interconnected exceeds limited address, node identification, and transaction tag spaces associated with each of the individual clusters.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: July 31, 2007
    Assignee: Newisys, Inc.
    Inventors: David Brian Glasco, Carl Zeitler, Rajesh Kota, Guru Prasadh, Richard R. Oehler
  • Patent number: 7222262
    Abstract: Techniques and devices are provided for injecting transactions within computer systems having a plurality of multi-processor clusters. Each cluster includes a plurality of nodes, including processors, a service processor and an interconnection controller interconnected by point-to-point intra-cluster links. The processors and the interconnection controller in each cluster make transactions via an intra-cluster transaction protocol. Inter-cluster links are formed between interconnection controllers of different clusters. Each of the processors and the interconnection controller in a cluster has a test interface for communicating with the service processor. The service processor is configured to make an injected transaction according to the intra-cluster transaction protocol via one of the test interfaces.
    Type: Grant
    Filed: August 5, 2003
    Date of Patent: May 22, 2007
    Assignee: Newisys, Inc.
    Inventors: Guru Prasadh, David Brian Glasco, Rajesh Kota, Scott Diesing