Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern is scanned into the scan chain using a shift clock operating at a first rate. The test pattern is then provided to combinatorial logic circuitry coupled to the scan chain. A response pattern is captured in the scan chain and then scanned from the scan chain using a shift clock operating at a second rate that is slower than the first rate. The response pattern is provided to the external tester using the same set of I/O pins and buffers operating in parallel.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with the storage circuit (110) and with the functional circuit modules (IP.i. The test controller (140, 150) is operable to dynamically schedule and trigger the tests in those sets, which promotes concurrent execution of tests in the functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain includes at least a first segment and a second segment. A first portion of a test pattern is scanned into the first segment by clocking a first scan cell of the first segment with an even clock while clocking a remainder of the plurality of scan cells in the first segment with an odd clock, in which the odd clock is out of phase with the even clock, in which the even clock and odd clock have a rate equal to a scan rate of the test pattern divided by an integer N. A second portion of the test pattern is scanned into the second segment by clocking the plurality of scan cells in the second segment with the odd clock, such that the second portion of the test pattern is not scanned into the first segment.

Abstract: Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency F1 and includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F1. Adapter module is coupled to tester and configured to receive M scan inputs at F1 and, in response, provide P scan inputs at clock frequency F2 to P scan input ports, and to receive Q scan outputs at F2 from Q scan output ports and, in response, provide N scan outputs at F1 to N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.

Abstract: Systems and methods for enabling scan testing of device-under-test (DUT) are disclosed. In an embodiment, a test system for scan testing the DUT, including P scan input ports and Q scan output ports, includes tester and adapter module. Tester operates at clock frequency F1 and includes M tester Input/Output (I/O) ports for providing M scan inputs and N tester I/O ports for receiving N scan outputs at F1. Adapter module is coupled to tester and configured to receive M scan inputs at F1 and, in response, provide P scan inputs at clock frequency F2 to P scan input ports, and to receive Q scan outputs at F2 from Q scan output ports and, in response, provide N scan outputs at F1 to N tester I/O ports, where ratio of M to P equals ratio of N to Q, and where each of M, N, P and Q are positive integers.

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements. Each packing element includes k number of flip-flops. Each flip-flop of the k number of flip-flops receives a scan output of the M scan outputs and a phase-shifted scan clock of the k number of phase-shifted scan clocks, and generates a slow scan output of the kM slow scan outputs.

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract: A circuit that facilitates faster diagnosis of plurality of logic circuits connected in a scan chain is provided. The circuit includes a first multiplexer that receives a scan data input. A flip-flop is coupled to an output of the first multiplexer and generates a scan pattern. An inverter generates an inverted feedback signal in response to the scan pattern. The inverted feedback signal is provided to the first multiplexer. A plurality of logic circuits is connected in a scan chain and generates a logic output in response to the scan pattern. A bypass multiplexer is coupled to the plurality of logic circuits. The bypass multiplexer generates a scan output in response to the logic output, the scan data input and a segment bypass input.

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes a scan compression architecture driven by a scan clock and generates M scan outputs, where M is an integer. A clock divider is configured to divide the scan clock by k to generate k number of phase-shifted scan clocks, where k is an integer. A packing logic is coupled to the scan compression architecture and generates kM slow scan outputs in response to the M scan outputs and the k number of phase shifted scan clocks. The packing logic further includes M number of packing elements and each packing element of the M number of packing elements receives a scan output of the M scan outputs. Each packing element includes k number of flip-flops and each flip-flop of the k number of flip-flops in a packing element receives a scan output of the M scan outputs.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.