Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract: A time borrowing domino circuit that includes complementary logic outputs and a multiplexor without incurring the time delays normally associated with complementary outputs and multiplexor function is described. A clock delay circuit is described which produces the trailing edge delay clock signal that drives the domino circuit. A domino circuit is described that may implement logical functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR and EXCLUSIVE-NOR. A multiplexor circuit is described for gating one of a number of logical inputs to a latch. And a latch is described having complementary outputs.

Abstract: A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.