Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

Abstract: A data storage system can have a hardware interposer connected inline between a plurality of controllers and a plurality of memories. A bus of the hardware interposer may be monitored with a security breach monitor of the hardware interposer to allow a deviation from a predetermined address range to be detected by the security breach monitor, which prompts the security breach monitor to block access through the hardware interposer for a first controller of the plurality of controllers.

Abstract: A dynamically reconfigurable computational storage drive (CSD) that facilitates parallel data management functionality for a plurality of associated memory devices. The CSD includes an FPGA device that is dynamically reconfigurable during operation of the CSD to provide configuration of a storage interface. Specifically, the FPGA device may be dynamically configured to provide one of a plurality of different communication protocols. A physical connector may be remapped to facilitate a communication protocol without reconnecting a memory device or CSD. The CSD may be provided as a rack-mounted device or a storage appliance for dynamic provision of data management functionality to data in a storage system comprising the CSD.

Abstract: An implementation of a device disclosed herein includes a field programmable gate array (FPGA) circuit and a non-volatile memory (NVM) configured external to the FPGA circuit and configured to communicate with an in-system programming (ISP) manager configured on the FPGA circuit, wherein the NVM is further configured to store one or more system parameters and one or more firmware images, wherein the ISP manager being configured to detect an ISP mode in response to receiving a signal from an ISP switch and executing an ISP state machine to update one or more FPGA CPU control registers with one or more of the system parameters and the one or more of the firmware images stored on the NVM.

Abstract: A power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to enable temporary power to be provided from the at least one energy storage device to a plurality of data storage devices upon a system power loss event. The power controller is further configured to receive a power loss indication signal associated with any individual one of the plurality of data storage devices and responsively enable power loss protection for the data storage device.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: A hybrid storage device includes a first storage medium configured to store data at a first speed and a second storage medium configured to store data at a second speed. The first storage medium may be a NAND flash storage medium, and the second storage medium may be disc storage medium. Partitions of the first storage medium are associated with partitions of the second storage medium to form at least two storage tiers. Each of the storage tiers may include different NAND partition capacities. The storage device further includes a peer to peer communication channel between the first storage medium and the second storage medium for moving data between a NAND partition and HDD partition. The storage device is accessible via a dual port SAS or PCIe interface.

Abstract: A system includes a direct current uninterruptible power supply (DC UPS) that receives an alternating current (AC) power input and provides a first DC power output. The system also includes a power distribution unit (PDU). The PDU receives the first DC power output from the DC UPS. The PDU converts the first DC power output into a second DC power output that supplies power to at least one component of information technology equipment (ITE) via a DC mating connector.

Abstract: A power management circuit includes at least one energy storage device and a power controller coupled to the at least one energy storage device. The power controller is configured to enable temporary power to be provided from the at least one energy storage device to a plurality of data storage devices upon a system power loss event. The power controller is further configured to receive a power loss indication signal associated with any individual one of the plurality of data storage devices and responsively enable power loss protection for the data storage device.

Abstract: A system includes a direct current uninterruptible power supply (DC UPS) that receives an alternating current (AC) power input and provides a first DC power output. The system also includes a power distribution unit (PDU). The PDU receives the first DC power output from the DC UPS. The PDU converts the first DC power output into a second DC power output that supplies power to at least one component of information technology equipment (ITE) via a DC mating connector.

Abstract: A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: A hybrid storage device includes a first storage medium configured to store data at a first speed and a second storage medium configured to store data at a second speed. The first storage medium may be a NAND flash storage medium, and the second storage medium may be disc storage medium. Partitions of the first storage medium are associated with partitions of the second storage medium to form at least two storage tiers. Each of the storage tiers may include different NAND partition capacities. The storage device further includes a peer to peer communication channel between the first storage medium and the second storage medium for moving data between a NAND partition and HDD partition. The storage device is accessible via a dual port SAS or PCIe interface.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: Implementations described and claimed herein provide a method and system for adaptive caching in a storage device. The method includes receiving an adaptive caching policy from a host for caching host read data and host write data in a hybrid drive using NAND cache, and allocating read cache for the host read data and write cache for the host write data in the NAND cache based on the adaptive caching policy. In some implementations, the method also includes iteratively performing an input/output (I/O) profiling operation to generate an I/O profile. An adaptive caching policy may be applied based on the I/O profile. When a unit time has completed, a new I/O profile may be compared with a current I/O profile. A new adaptive caching policy is applied based on determining the new I/O profile is different than the current I/O profile.

Abstract: A method includes configuring a first set of blocks of a plurality of blocks of an IC chip as secure data blocks, and configuring a second set of blocks of the plurality of blocks as non-secure data blocks. The method further includes receiving a test mode entry request in the IC chip. In response to the IC chip receiving the test mode entry request, carrying out a data-initialization operation on the plurality of blocks independently of whether any blocks of the plurality of blocks are configured as the secure data blocks or the non-secure data blocks. An IC chip data output is disabled during the data-initialization operation.

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.

Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.