Patents by Inventor Rajesh Mittal
Rajesh Mittal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240111799Abstract: Various embodiments of the present invention provide methods, apparatus, systems, computing devices, computing entities, and/or the like for performing predictive data analysis operations. Certain embodiments of the present invention utilize systems, methods, and computer program products that perform predictive data analysis operations by generating a hybrid class for a multi-party communication transcript data object associated with a predictive entity utilizing a hybrid space classification machine learning model, generating a machine learning-based risk score utilizing a hybrid-class-based risk scoring machine learning model, and generating a hierarchical-workflow risk score using a hierarchical risk score adjustment workflow.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Rajesh Sabapathy, Gourav Awasthi, Rebin Raju, Chirag Mittal, Sharenna D. Gonzalez
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Patent number: 11899063Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: GrantFiled: June 29, 2022Date of Patent: February 13, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Publication number: 20220326303Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 11408936Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: GrantFiled: July 6, 2020Date of Patent: August 9, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 10832668Abstract: Techniques for dynamically maintaining speech processing data on a local device for frequently input commands are described. One or more devices receive speech processing data specific to one or more commands associated with system input frequencies satisfying an input frequency threshold. The device(s) then receives input audio corresponding to an utterance and generate input audio data corresponding thereto. The device(s) performs speech recognition processing on input audio data to generate input text data using a portion of the received speech processing data. The device(s) determines a probability score associated with the input text data and determines the probability score satisfies a threshold probability score. The device(s) then performs natural language processing on the input text data to determine the command using a portion of the speech processing data. The device(s) then outputs audio data responsive to the command.Type: GrantFiled: September 19, 2017Date of Patent: November 10, 2020Assignee: Amazon Technologies, Inc.Inventors: David William Devries, Rajesh Mittal
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Publication number: 20200333397Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: ApplicationFiled: July 6, 2020Publication date: October 22, 2020Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 10739402Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: GrantFiled: July 18, 2018Date of Patent: August 11, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 10515637Abstract: Techniques for dynamically maintaining speech processing data on a local device for frequently input commands are described. A system determines a usage history associated with a user profile. The usage history represents at least a first command. The system determines the first command is associated with an input frequency that satisfies an input frequently threshold. The system also determines the first command is missing from first speech processing data stored by a device associated with the user profile. The system then generates second speech processing data specific to the first command and sends the second speech processing data to the device.Type: GrantFiled: September 19, 2017Date of Patent: December 24, 2019Assignee: AMAZON TECHNOLOGIES, INC.Inventors: David William Devries, Rajesh Mittal
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Patent number: 10274538Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: October 2, 2017Date of Patent: April 30, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20180321311Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: ApplicationFiled: July 18, 2018Publication date: November 8, 2018Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 10060979Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: GrantFiled: August 2, 2016Date of Patent: August 28, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Patent number: 9970987Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: GrantFiled: August 17, 2016Date of Patent: May 15, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Publication number: 20180045778Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: October 2, 2017Publication date: February 15, 2018Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Publication number: 20180038910Abstract: A scan chain may be formed throughout an integrated circuit in which the scan chain is coupled to a set of pins via bi-directional input/output (I/O) buffers. A state machine may be provided to control the scan chain. Decoding logic may monitor states and transitions between states and generate pseudo static control signals in response to certain states and transition sequences in order to free up test pins for use as additional scan data I/O pins using a single JTAG IR. A test pattern may be received from an external tester using the set of I/O pins and buffers operating in parallel. The test pattern may then be provided to combinatorial logic circuitry coupled to the scan chain. A response pattern may be captured in the scan chain. The response pattern may then be provided to the external tester using the same set of I/O pins and buffers operating in parallel.Type: ApplicationFiled: August 2, 2016Publication date: February 8, 2018Inventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Publication number: 20170315174Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: ApplicationFiled: April 29, 2016Publication date: November 2, 2017Inventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Patent number: 9791505Abstract: An integrated circuit, comprising functional circuitry and testing circuitry. A first set of pads is operable in a first state for communicating testing signals to the testing circuitry and operable in a second state for communicating input/output signals to the functional circuitry. A second set of pads, differing from the first set of pads, is operable in the second state for communicating testing signals to the testing circuitry for testing signals associated in the second state with the first set of pads.Type: GrantFiled: April 29, 2016Date of Patent: October 17, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Prakash Narayanan, Rajesh Mittal, Rajat Mehrotra
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Patent number: 9772376Abstract: An integrated circuit with functional circuitry and testing circuitry, the testing circuitry having a state machine operable in a plurality of different states. The integrated circuit also has a pin for receiving a signal, wherein the state machine is operable to transition between states in response to a change in level of the signal. Circuitry couples the signal of the pin, in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry maintains the signal in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also during the second time period, circuitry couples data received at the pin to a destination circuit other than the state machine, wherein the destination circuit is operable to perform plural successive scan tests using data from the pin without a power on reset of the functional circuitry.Type: GrantFiled: April 29, 2016Date of Patent: September 26, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mudasir Shafat Kawoosa, Rajesh Mittal
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Publication number: 20160356849Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: ApplicationFiled: August 17, 2016Publication date: December 8, 2016Inventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Patent number: 9448284Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: GrantFiled: May 8, 2014Date of Patent: September 20, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal
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Publication number: 20150323596Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.Type: ApplicationFiled: May 8, 2014Publication date: November 12, 2015Applicant: Texas Instruments IncorporatedInventors: Sreenath Narayanan Potty, Rajesh Mittal, Mudasir Shafat Kawoosa, Vivek Singhal