Patents by Inventor RAJESH NAYAK

RAJESH NAYAK has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200208857
    Abstract: One implementation of the present disclosure is a method of providing multi-dimensional load data to a user. The method includes generating, by a processing circuit, a user interface that enables a user to configure one or more components in one or more dimensions; receiving, by the processing circuit, a user input requesting load data in a first dimension; generating, by the processing circuit, first dimensional load data for each component in the first dimension; and presenting, by the processing circuit, the first dimensional load data to the user.
    Type: Application
    Filed: December 31, 2018
    Publication date: July 2, 2020
    Applicant: Johnson Controls Technology Company
    Inventors: Rajesh Nayak, Abhigyan Chatterjee, Barkha Shah, Shailesh Tavate
  • Publication number: 20200142365
    Abstract: A building management system includes one or more processing circuits. The one or more processing circuits are configured to receive, from a physical building device of a building, environmental inputs and environmental outputs of the physical building device; generate a building device digital twin for the physical building device based on the received environmental inputs and the received environmental outputs; generate a predicted future performance of the physical building device based on the building device digital twin; and generate a recommendation based on the predicted future performance of the physical building device, the recommendation indicating one or more changes to implement on the physical building device. The building device digital twin is a model for predicting the behavior of the physical building device ore changes to implement on the physical building device.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 7, 2020
    Inventors: Vikas Sharma, Sudhanshu Dixit, Ankur Thareja, Rajesh Nayak, Harpreet Singh Virdi, Anil Kumar, Rajeev T. Singh
  • Patent number: 10326013
    Abstract: A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 18, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Publication number: 20180145171
    Abstract: An integrated circuit (IC) structure may include one or more trench-based semiconductor devices, e.g., field-effect transistors (trench FETs), having a front-side drain contact. Each semiconductor device may include an epitaxy layer, a doped source region in the epitaxy layer, a front-side source contact coupled to the source region, a poly gate formed in a trench in the epitaxy layer, and a front-side drain contact extending through the poly gate trench and isolated from the poly gate. The device may define a drift region from the poly gate/source region intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extends into an underlying bulk substrate or transition layer. The depth of the front-side drain contact may be selected to influence the breakdown voltage of the respective device. In addition, the front-side drain contacts may allow the IC structure to be flip-chip mounted or packaged.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 24, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Publication number: 20180145170
    Abstract: A method is provided for forming an integrated circuit (IC) structure including trench-based semiconductor devices, e.g., trench FETs, having front-side drain contacts. The method may include forming an epitaxy region, forming a poly gate trench in the epitaxy region, forming a drain contact trench through the poly gate trench and extending below the poly gate trench, forming a poly gate in the poly gate trench, forming a front-side drain contact in the drain contact trench, and forming a source region in the epitaxy region adjacent the poly gate. The device may define a drift region from the poly gate/source intersection to the front-side drain contact. The drift region may be located within the epitaxy layer, without extending into an underlying substrate or transition layer. The front-side drain contact depth may be selected to influence the device breakdown voltage. The front-side drain contacts may allow flip-chip mounting of the IC structure.
    Type: Application
    Filed: November 21, 2017
    Publication date: May 24, 2018
    Applicant: Microchip Technology Incorporated
    Inventors: Greg Dix, Jina Shumate, Eric Peterson, Rajesh Nayak
  • Publication number: 20070269814
    Abstract: A method of determining the presence and level of microorganisms and/or chemicals in samples taken from generally any non-laboratory substance or environment. The method preferably comprises one or a combination of the steps of (a) prescreening for threshold levels of targeted microorganisms and/or (b) confirming the presence of targeted microorganisms or chemicals by mass spectrometry fingerprint analysis.
    Type: Application
    Filed: November 10, 2006
    Publication date: November 22, 2007
    Applicant: LITMUS, L.L.C.
    Inventors: JON WILKES, DAN BUZATU, DWIGHT MILLER, DANIEL CURTIS, MARK DIGGS, RAJESH NAYAK, FATEMEH RAFII, JOHN SUTHERLAND, RANDAL TUCKER