Patents by Inventor Rajesh Neermarga

Rajesh Neermarga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277344
    Abstract: There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the data, the data is stored in a FIM cache and moved from the FIM cache to the relevant physical layer to be programmed to the destination block. Because data is not being transferred to the system memory, the latency and bandwidth associated with relocating data may be decreased.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: April 15, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Narendra Darapureddy, Jacob Albons, Ramanathan Muthiah, Rajesh Neermarga
  • Publication number: 20240329880
    Abstract: There is a large latency and controller bandwidth associated with moving data between dies or between memory devices. The controller includes one or more flash interface modules (FIMs) that are utilized to write data to the memory device and read data from the memory device. Each of the one or more FIMs includes one or more switches. Each switch is utilized to transfer data from a source block to a destination block. Likewise, rather than using a memory external to the FIM to cache the data, the data is stored in a FIM cache and moved from the FIM cache to the relevant physical layer to be programmed to the destination block. Because data is not being transferred to the system memory, the latency and bandwidth associated with relocating data may be decreased.
    Type: Application
    Filed: July 6, 2023
    Publication date: October 3, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Narendra DARAPUREDDY, Jacob ALBONS, Ramanathan MUTHIAH, Rajesh NEERMARGA
  • Patent number: 9875085
    Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Rishi Mukhopadhyay, Abhijeet Manohar, Rajesh Neermarga
  • Publication number: 20170031656
    Abstract: A memory system and method are provided for generating a seed value. In one embodiment, a memory system identifies a random defect in a memory die and, in accordance with the identified random defect in the memory die, generates a seed value, wherein with the generated seed value a random number can be generated. Other embodiments are provided, which can be used alone or in combination with one another.
    Type: Application
    Filed: July 28, 2015
    Publication date: February 2, 2017
    Applicant: SanDisk Technologies Inc.
    Inventors: Rishi Mukhopadhyay, Abhijeet Manohar, Rajesh Neermarga