Patents by Inventor Rajesh Parthasarathy

Rajesh Parthasarathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170364476
    Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
    Type: Application
    Filed: June 30, 2017
    Publication date: December 21, 2017
    Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva, Mohammad Abdallah
  • Patent number: 9043521
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: May 26, 2015
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Patent number: 8838935
    Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
  • Publication number: 20140136746
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Publication number: 20140032881
    Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva
  • Publication number: 20140032624
    Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
    Type: Application
    Filed: September 30, 2013
    Publication date: January 30, 2014
    Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva
  • Publication number: 20130290392
    Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 31, 2013
    Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva
  • Patent number: 8423682
    Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: April 16, 2013
    Assignee: Intel Corporation
    Inventors: Sham M. Datta, Robert Greiner, Frank Binns, Keshavan Tiruvallur, Rajesh Parthasarathy, Madhavan Parthasarathy
  • Patent number: 8312198
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: November 13, 2012
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnandan Kaushik, Luke Hood
  • Publication number: 20120124264
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APlC) is interfaced via a set of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Application
    Filed: January 24, 2012
    Publication date: May 17, 2012
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnanda Kaushik, Luke Hood
  • Publication number: 20120079232
    Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
  • Patent number: 8103816
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: January 24, 2012
    Assignee: Intel Corporation
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnanda Kaushik, Luke Hood
  • Publication number: 20100106875
    Abstract: A technique to enable efficient interrupt communication within a computer system. In one embodiment, an advanced programmable interrupt controller (APIC) is interfaced via a set of of bits within an APIC interface register using various interface instructions or operations, without using memory-mapped input/output (MMIO).
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Keshavan Tiruvallur, Rajesh Parthasarathy, James B. Crossland, Shivnanda Kaushik, Luke Hood
  • Publication number: 20080071851
    Abstract: Method, apparatus, and program means for performing a dot-product operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources store to a storage location a result value equal to a dot-product of at least two operands.
    Type: Application
    Filed: September 20, 2006
    Publication date: March 20, 2008
    Inventors: Ronen Zohar, Mark Seconi, Rajesh Parthasarathy, Srinivas Chennupaty, Mark Buxton, Chuck Desylva
  • Patent number: 7305592
    Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: December 4, 2007
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Andrew V. Anderson, Steven M. Bennett, Jason Brandt, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain K├Ągi, Sanjoy K. Mondal, Rajesh Parthasarathy, Dion Rodgers, Lawrence O. Smith, Richard A. Uhlig
  • Publication number: 20070174587
    Abstract: Apparatus and systems, as well as methods and articles, may operate to detect an input/output access operation associated with a configuration memory address and a first memory address bit size. The configuration memory address and associated configuration data may be combined into a packet having a second memory address bit size (e.g., 64 bits) greater than the first memory address bit size (e.g., 32 bits). The packet may be used to establish compatibility for legacy operating systems that attempt to communicate with peripheral component interconnect (PCI) interface-based peripherals, and similar platform devices, that have been integrated into the same package as the processor.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 26, 2007
    Inventors: Sham Datta, Robert Greiner, Frank Binns, Keshavan Tiruvallur, Rajesh Parthasarathy, Madhavan Parthasarathy
  • Publication number: 20070156986
    Abstract: Embodiments of apparatuses, methods, and systems for guests to access memory mapped devices are disclosed. In one embodiment, an apparatus includes evaluation logic and exit logic. The evaluation logic is to determine, in response to an attempt of a guest to access a device using a memory address mapped to the device and based on an access type, whether the access is allowed. The exit logic is to transfer control to a host if the evaluation logic determines that the access is not allowed.
    Type: Application
    Filed: December 30, 2005
    Publication date: July 5, 2007
    Inventors: Gilbert Neiger, Andrew Anderson, Steven Bennett, Rajesh Madukkarumukumana, Richard Uhlig, Rajesh Parthasarathy, Sebastian Schoenberg
  • Publication number: 20070006230
    Abstract: Embodiments of apparatuses and methods for guest processes to access registers are disclosed. In one embodiment, an apparatus includes an interface to a first register, shadow logic, evaluation logic, and exit logic. The shadow logic is to, in response to a guest attempt to write data to the first register, cause the data to be written to a second register. The evaluation logic is to determine, based on the value of the data, whether to transfer control to a host in response to the guest attempt. The exit logic is to transfer control to the host after the data is written to the second register if the evaluation logic determines to transfer control.
    Type: Application
    Filed: June 30, 2005
    Publication date: January 4, 2007
    Inventors: Gilbert Neiger, Richard Uhlig, Dion Rodgers, Jason Brandt, Rajesh Parthasarathy
  • Publication number: 20060005084
    Abstract: In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 5, 2006
    Inventors: Gilbert Neiger, Andrew Anderson, Steven Bennett, Jason Brandt, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Sanjoy Mondal, Rajesh Parthasarathy, Dion Rodgers, Lawrence Smith, Richard Uhlig