Patents by Inventor Rajesh Pathak

Rajesh Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240290965
    Abstract: A discharged electrochemical cell as described herein comprises an electrochemically reactive metal-containing cathode (e.g., Li, Na, Mg, or Zn; preferably Li) and a layered anode with an electrolyte therebetween. The layered anode comprises a conductive substrate and a reactive film of a metal, a semimetal, a metal oxide, or a semimetal oxide on the surface of the substrate. The reactive film is capable of reversibly alloying with, reversibly forming a mixed phase with, or reversibly reacting with, metal from cathode during charging of cell, and releasing the metal back to the cathode during discharge of the cell.
    Type: Application
    Filed: February 8, 2024
    Publication date: August 29, 2024
    Applicant: UCHICAGO ARGONNE, LLC
    Inventors: Michael J. Counihan, Sanja Tepavcevic, Pallab Barai, Venkat Srinivasan, Anil U. Mane, Rajesh Pathak, Jeffrey W. Elam
  • Publication number: 20240266527
    Abstract: A coated cathode material including high-nickel lithium cathode and a method of producing the same by atomic layer deposition.
    Type: Application
    Filed: February 6, 2023
    Publication date: August 8, 2024
    Applicant: UCHICAGO ARGONNE, LLC
    Inventors: Jihyeon Gim, Anil U. Mane, Jinhyup Han, Seoung-Bum Son, Pragathi Darapaneni, Eungje Lee, Khalil Amine, Jeffrey W. Elam, Jason R. Croy, Rajesh Pathak
  • Patent number: 6359477
    Abstract: A buffer circuit includes a chain of a plurality of inverters. A first inverter has transistors with a size to present a first predetermined capacitive loading at its input. This is selected with regard to the target operating frequency of the driving circuit (typically a flip-flop) and the transistor size selected for this driving circuit. Each inverter has transistors with a size a predetermined size factor greater than the transistors of a preceding inverter. The first inverter has transistors the size factor larger than the driving circuit. The size factor is preferably 3. The number of inverters in the chain is selected so that the last inverter has transistors with a size to drive its output capacitive loading with a maximum rise and fall time corresponding to the target frequency. If the number of inverters is even, then the buffer input is connected to a normal output of the driving circuit.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: March 19, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Rajesh Pathak