Abstract: Method and apparatus for generating system clock synchronization pulses using a Phase Locked Loop (PLL) lock detect signal are provided. The method includes utilizing a clock lock detect signal indicative that a system clock is synchronized with an internal clock, and determining an initial count value. Then, start counting beginning at a first rising edge of the system clock after the clock lock detect signal is generated, the counting starting with the initial count value. The method further includes generating a synchronization pulse (syncnp) when the counting ends, where the syncnp indicates the beginning of the next system clock cycle, and continue generating syncnps separated by one system clock cycle so as to continue indicating the beginning of the next system clock cycle. The method further guarantees stopping the syncnp generation when the lock detect is inactive indicating that the internal clock and the system clock are not synchronized.

Abstract: Method and apparatus for generating system clock synchronization pulses using a Phase Locked Loop (PLL) lock detect signal are provided. The method includes utilizing a clock lock detect signal indicative that a system clock is synchronized with an internal clock, and determining an initial count value. Then, start counting beginning at a first rising edge of the system clock after the clock lock detect signal is generated, the counting starting with the initial count value. The method further includes generating a synchronization pulse (syncnp) when the counting ends, where the syncnp indicates the beginning of the next system clock cycle, and continue generating syncnps separated by one system clock cycle so as to continue indicating the beginning of the next system clock cycle. The method further guarantees stopping the syncnp generation when the lock detect is inactive indicating that the internal clock and the system clock are not synchronized.

Abstract: A method and tool for simulating a multiple input signature register for a memory test application is provided. Further, a method and tool for signature simulation based on a configuration, type, and/or size of a memory structure is provided. Further, a method and tool for multiple input signature register simulation for a memory built-in self test application is provided.

Abstract: A method of transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects includes designing a functional block based on a set of design considerations; generating a parallel functional pattern for testing the functional block; and translating the parallel functional pattern into a serial pattern. An apparatus for transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects, comprising a functional block designed based on a set of design considerations and comprising a scan boundary, the scan boundary comprising a scan in chain and a scan out chain, a parallel functional pattern for testing the functional block; and software for translating the parallel functional pattern into a serial pattern that is fed into the scan in chain, evaluated, and fed out of the scan out chain.

Abstract: A method and tool for simulating a multiple input signature register for a memory test application is provided. Further, a method and tool for signature simulation based on a configuration, type, and/or size of a memory structure is provided. Further, a method and tool for multiple input signature register simulation for a memory built-in self test application is provided.