Abstract: Methods and server systems for computing fraud risk scores for various merchants associated with an acquirer described herein. The method performed by a server system includes accessing merchant-related transaction data including merchant-related transaction indicators associated with a merchant from a transaction database. Method includes generating a merchant-related transaction features based on the merchant-related indicators. Method includes generating via risk prediction models, for a payment transaction with the merchant, merchant health and compliance risk scores, merchant terminal risk scores, merchant chargeback risk scores, and merchant activity risk scores based on the merchant-related transaction features. Method includes facilitating transmission of a notification message to an acquirer server associated with the merchant.

Abstract: A device may receive, in near-real time, unstructured data associated with an application or a system, and may extract textual data from the unstructured data. The device may parse the textual data to generate parsed textual data, and may perform natural language processing on the parsed textual data to generate processed textual data. The device may process the processed textual data, with a clustering model, to identify topical data associated with the processed textual data, and may process the topical data, with a classification model, to group the topical data into categories. The device may generate a knowledge graph based on the categories, and may store the knowledge graph in a data structure. The knowledge graph may enable the device to provide answers to questions associated with the application or the system.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of silicon-containing material on a semiconductor substrate. The methods may include performing a post-formation treatment on the layer of silicon-containing material to yield a treated layer of silicon-containing material. The methods may include contacting the treated layer of silicon-containing material with an adhesion agent. The methods may include forming a layer of a resist material on the treated layer of silicon-containing material.

Abstract: Methods for depositing a hardmask with ions implanted at different tilt angles are described herein. By performing ion implantation to dope an amorphous carbon hardmask at multiple tilt angles, an evenly distributed dopant profiled can be created. The implant tilt angle will determine a dopant profile that enhances the carbon hardmask hardness.

Abstract: A method of forming a semiconductor device may include forming a plurality of fins extending from a buried oxide layer, wherein a masking layer is disposed atop each of the plurality of fins, and performing a high-temperature ion implant to the semiconductor device. The method may further include performing an etch process to remove the masking layer from atop each of the plurality of fins, wherein the etch process does not remove the buried oxide layer.

Abstract: Exemplary methods of semiconductor processing may include forming a layer of amorphous silicon on a semiconductor substrate. The layer of amorphous silicon may be characterized by a first amount of hydrogen incorporation. The methods may include performing a beamline ion implantation process or plasma doping process on the layer of amorphous silicon. The methods may include removing hydrogen from the layer of amorphous silicon to a second amount of hydrogen incorporation less than the first amount of hydrogen incorporation.

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

Abstract: Methods of forming a silicon hardmask are disclosed. In one example, a method may include forming a silicon mask over a device layer, forming a carbon mask over the silicon mask, and forming an opening through the carbon mask. The method may further include forming an oxide layer within the opening by performing an ion implantation process to an upper surface of the silicon mask.

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 ?m or more using larger tilt angles.

Abstract: A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.

Abstract: A method to form a 2-Dimensional transistor channel may include depositing an amorphous layer comprising a 2-dimensional material, implanting an implant species into the amorphous layer; and annealing the amorphous layer after the implanting. As such, the amorphous layer may form a doped crystalline layer.

Abstract: A system and method that allows higher energy implants to be performed, wherein the peak concentration depth is shallower than would otherwise occur is disclosed. The system comprises an ion source, an accelerator, a platen and a platen orientation motor that allows large tilt angles. The system may be capable of performing implants of hydrogen ions at an implant energy of up to 5 MeV. By tilting the workpiece during an implant, the system can be used to perform implants that are typically performed at implant energies that are less than the minimum implant energy allowed by the system. Additionally, the resistivity profile of the workpiece after thermal treatment is similar to that achieved using a lower energy implant. In certain embodiments, the peak concentration depth may be reduced by 3 ?m or more using larger tilt angles.

Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.

Abstract: A method of forming surface features in a hardmask layer, including etching a first surface feature into the hardmask layer, the first surface feature having a first critical dimension, performing an ion implantation process on the first surface feature to make the first surface feature resistant to subsequent etching processes, etching a second surface feature into the hardmask layer adjacent the first surface feature, wherein the first critical dimension is preserved.

Abstract: Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.