Abstract: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Abstract: Identifying computer system markers to understand computer system performance, in one aspect, may comprise identifying a set of executions of applications indicative of computer performance based on first values associated with a first set of artifacts in the set of executions. Two subsets of executions from said identified set of executions are selected based on second values associated with a second set of artifacts in the set of executions. One or more markers are identified by determining one or more third set of artifacts from the two subsets of executions that have an associated third value that is different in a first of the two subsets from a second of the two subsets of executions according to a criterion.

Abstract: Techniques for identifying one or more communities in an information network are provided. The techniques include collecting one or more nodes and one or more edges from an information network, performing a random walk on the one or more nodes to produce a sequence of one or more nodes, creating a sequence database from one or more sequences produced via random walk, and mining the sequence database to determine one or more patterns in the network, wherein the one or more patterns identify one or more communities in the information network.

Abstract: Techniques for searching multi-dimensional data are provided. The techniques include providing a parallelization framework for a search algorithm, wherein the search algorithm exposes one or more architecture-sensitive tunable optimization parameters, and using the one or more architecture-sensitive tunable optimization parameters to tune the search algorithm to search multi-dimensional data in any underlying architecture.

Abstract: Techniques for identifying one or more communities in an information network are provided. The techniques include collecting one or more nodes and one or more edges from an information network, performing a random walk on the one or more nodes to produce a sequence of one or more nodes, creating a sequence database from one or more sequences produced via random walk, and mining the sequence database to determine one or more patterns in the network, wherein the one or more patterns identify one or more communities in the information network.

Abstract: Techniques for optimizing sparse matrix-vector multiplication (SpMV) on a graphics processing unit (GPU) are provided. The techniques include receiving a sparse matrix-vector multiplication, analyzing the sparse matrix-vector multiplication to identify one or more optimizations, wherein analyzing the sparse matrix-vector multiplication to identify one or more optimizations comprises analyzing a non-zero pattern for one or more optimizations and determining whether the sparse matrix-vector multiplication is to be reused across computation, optimizing the sparse matrix-vector multiplication, wherein optimizing the sparse matrix-vector multiplication comprises optimizing global memory access, optimizing shared memory access and exploiting reuse and parallelism, and outputting an optimized sparse matrix-vector multiplication.

Abstract: Techniques for searching multi-dimensional data are provided. The techniques include providing a parallelization framework for a search algorithm, wherein the search algorithm exposes one or more architecture-sensitive tunable optimization parameters, and using the one or more architecture-sensitive tunable optimization parameters to tune the search algorithm to search multi-dimensional data in any underlying architecture.

Abstract: Provided is a method that enables an interpretive engine to execute in a non-homogeneous, multiple processor architecture. Am interpretive engine is modified to identify code native to a target processor that is executing an ISA different than the ISA of the processor executing the interpretive engine. An intermediate function is called to correlate the native code with a processor type and a target processor is identified. A context is created for the native code and the context is either transmitted to the target processor or stored in a memory location such that the target processor may retrieve the context. Once the context is transmitted, the target processor executes the task. Results are either transmitted to the originating processor or placed in memory such that the originating processor can access the result and the originating processor is signaled of the completion of the task.

Abstract: In a virtual machine environment, the invention enables creation of a long running, reusable, virtual machine are disclosed. The environment includes a shared heap where requisite runtime code to bring the virtual machine into a ‘ready’ mode are loaded, linked, verified, initialized and compiled. Subsequent virtual machines are started and jointly use the shared heap. Applications create their objects in ‘private heaps’ that are exclusively reserved for the respective applications. At the end of execution of an application, each private heap is reinitialized. Static initializers are run in a persistent area of each private heap. This persistent area is reset to its initial values in between execution of applications. This obviates the need to terminate the virtual machine.