Patents by Inventor Rajesh Rengarajan
Rajesh Rengarajan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9355887Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: GrantFiled: January 12, 2012Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Publication number: 20120104511Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: ApplicationFiled: January 12, 2012Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 8097516Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: GrantFiled: July 9, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 7943486Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: May 6, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7883948Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.Type: GrantFiled: May 14, 2009Date of Patent: February 8, 2011Assignee: International Business Machines CorporationInventors: Brian J. Greene, Rajesh Rengarajan
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Publication number: 20090236640Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.Type: ApplicationFiled: May 14, 2009Publication date: September 24, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, Rajesh Rengarajan
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Patent number: 7572689Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.Type: GrantFiled: November 9, 2007Date of Patent: August 11, 2009Assignee: International Business Machines CorporationInventors: Brian J. Greene, Rajesh Rengarajan
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Publication number: 20090121295Abstract: Methods and structures for relieving stresses in stressed semiconductor liners. A stress liner that enhances performance of either an NFET or a PFET is deposited over a semiconductor to cover the NFET and PFET. A disposable layer is deposited to entirely cover the stress liner, NFET and PFET. This disposable layer is selectively recessed to expose only the single stress liner over a gate of the NFET or PFET that is not enhanced by such stress liner, and then this exposed liner is removed to expose a top of such gate. Remaining portions of the disposable layer are removed, thereby enhancing performance of either the NFET or PFET, while avoiding degradation of the NFET or PFET not enhanced by the stress liner. The single stress liner is a tensile stress liner for enhancing performance of the NFET, or it is a compressive stress liner for enhancing performance of the PFET.Type: ApplicationFiled: November 9, 2007Publication date: May 14, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. Greene, Rajesh Rengarajan
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Patent number: 7473607Abstract: A method of manufacturing a device includes doping a low voltage threshold area and a high voltage threshold area. Gate structures are formed over the low voltage threshold and high voltage threshold areas while protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected. Siliciding includes depositing metal on the gate of the high voltage threshold area and annealing the metal, the metal is deposited either by CVD or sputtering followed by anneal to fully suicide the gate structure of the high voltage threshold area. The metal, preferably cobalt or nickel is deposited to a thickness of approximately 500 ?, annealed for about 3 minutes at about 400° C.Type: GrantFiled: July 6, 2005Date of Patent: January 6, 2009Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Rajesh Rengarajan
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Patent number: 7462525Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: October 25, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080290379Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: ApplicationFiled: July 9, 2008Publication date: November 27, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Publication number: 20080206958Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: May 6, 2008Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080044987Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: October 25, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo Fischetti, John Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080044966Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: October 25, 2007Publication date: February 21, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo Fischetti, John Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul Solomon, Chun-yung Sung, Min Yang
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Publication number: 20080036028Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: ApplicationFiled: October 23, 2007Publication date: February 14, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 7314790Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: December 18, 2006Date of Patent: January 1, 2008Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Publication number: 20070099367Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: December 18, 2006Publication date: May 3, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo Fischetti, John Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul Solomon, Chun-yung Sung, Min Yang
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Publication number: 20070040235Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: ApplicationFiled: August 19, 2005Publication date: February 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Publication number: 20070020865Abstract: A method of manufacturing a device and the device. The device includes doping a low voltage threshold area and a high voltage threshold area. The method further includes forming gate structures over the low voltage threshold area and the high voltage threshold area and protecting the gate structure over the low voltage threshold area. A silicidation process is performed over the high voltage threshold area while the gate structure over the low voltage threshold area remains protected.Type: ApplicationFiled: July 6, 2005Publication date: January 25, 2007Applicant: International Business Machines CorporationInventors: Xiangdong Chen, Rajesh Rengarajan
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Patent number: 7161169Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: November 3, 2004Date of Patent: January 9, 2007Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Leong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang