Abstract: Embodiments of the disclosure include swellable smart gel sealants and methods of using smart gel sealants. In certain embodiments, the smart gel sealants reversibly swell when exposed to a certain trigger, such as carbonic acid and/or sulfuric acid. In specific embodiments, the smart gel is comprised within a cement composition.

Abstract: Embodiments of the disclosure include swellable smart gel sealants and methods of using smart gel sealants. In certain embodiments, the smart gel sealants reversibly swell when exposed to a certain trigger, such as carbonic acid and/or sulfuric acid. In specific embodiments, the smart gel is comprised within a cement composition.

Abstract: A computer implemented method for prediction of geomechanical performance including productivity index decline and completion integrity for a well or a hydrocarbon reservoir using a geomechanics informed machine intelligence (GIMI) algorithm. The method includes running a geomechanical reservoir simulator to generate training datasets for the hydrocarbon reservoir and incorporating physical models and identified variables into the GIMI algorithm. The method further includes training a neural network of the GIMI algorithm by using correlated training datasets that correlate to the physical models to produce a resulting prediction model and performing sensitivity analysis on the resulting prediction model. Additionally, the method includes identifying dominant variables for damage mechanisms through design of experiment statistics and performing history matching and blind test on the resulting prediction model.

Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Abstract: A lateral FET cell is formed in a body of semiconductor material. The lateral FET cell includes a super junction structure formed in a drift region between a drain contact and a body region. The super junction structure includes a plurality of spaced apart filled trenches bounding in part a multiplicity of striped doped regions having opposite or alternating conductivity types.

Abstract: In one embodiment, a lateral FET cell is formed in a body of semiconductor material. The body of semiconductor material includes alternating layers of opposite conductivity type that extend between a trench drain region and a trench gate structure. The trench gate structure controls at least one sub-surface channel region. The body of semiconductor material provides sub-surface drift regions to reduce on resistance without increasing device area.

Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Abstract: In one embodiment, a lateral FET structure (30) is formed in a body of semiconductor material (32). The structure (30) includes a plurality non-interdigitated drain regions (39) that are coupled together with a conductive layer (57), and a plurality of source regions (34) that are coupled together with a different conductive layer (51). One or more interlayer dielectrics (53,54) separate the two conductive layers (51,57). The individual source regions (34) are absent small radius fingertip regions.

Abstract: A semiconductor device (10, 40) is formed to have a well (19) in a substrate (11). The well and the substrate have the same doping type, for example both P-type or both N-type. Low resistance contact regions (26, 27) of a second conductivity type are formed to at least abut the well. A drain (17) is formed within one low resistance contact region. A source (12) is formed in the substrate and laterally displaced from the other low resistance contact region. A buried layer (21, 22, 23) is formed laterally across the well.

Abstract: A method of forming a semiconductor device (10, 40, 45, 50) forms a plurality of P and N stripes (16,17) within a first region (12) that is formed with an opposite conductivity to a substrate (11). The plurality of P and N stripes assist in providing a low on-resistance. A portion (15) of the first region underlies the P and N stripes and protects the semiconductor device from high voltages applied to the drain. A base layer (41) and a cap layer (48) further reduce the on-resistance of the semiconductor device.