Patents by Inventor Rajesh Subraya Aiyandra
Rajesh Subraya Aiyandra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230077469Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.Type: ApplicationFiled: October 17, 2022Publication date: March 16, 2023Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Patent number: 11495567Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.Type: GrantFiled: August 17, 2020Date of Patent: November 8, 2022Assignee: Dialog Semiconductor (UK) LimitedInventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Patent number: 11309255Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.Type: GrantFiled: March 26, 2020Date of Patent: April 19, 2022Assignee: Dialog Semiconductor (UK) LimitedInventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
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Publication number: 20200395325Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.Type: ApplicationFiled: August 17, 2020Publication date: December 17, 2020Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Patent number: 10797012Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.Type: GrantFiled: August 25, 2017Date of Patent: October 6, 2020Assignee: Dialog Semiconductor (UK) LimitedInventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Publication number: 20200227356Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.Type: ApplicationFiled: March 26, 2020Publication date: July 16, 2020Inventors: Jesus Mennen Belonio, JR., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
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Patent number: 10636742Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.Type: GrantFiled: September 28, 2017Date of Patent: April 28, 2020Assignee: Dialog Semiconductor (US) LimitedInventors: Jesus Mennen Belonio, Jr., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
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Patent number: 10607912Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.Type: GrantFiled: July 30, 2019Date of Patent: March 31, 2020Assignee: Dialog Semiconductor (UK) LimitedInventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Publication number: 20190355641Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Patent number: 10396004Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.Type: GrantFiled: January 25, 2018Date of Patent: August 27, 2019Assignee: Dialog Semiconductor (UK) LimitedInventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Publication number: 20190259689Abstract: A method of fabricating an integrated circuit package having improved heat dissipation is described. A re-routable clip is provided having a central portion and a plurality of leads surrounding the central portion. A die is attached to an underside of the central portion of the re-routable clip. The die and the leads of the re-routable clip are attached to a substrate. The die and the leads are encapsulated with a mold compound wherein a top surface of the central portion of the re-routable clip is exposed by the mold compound. The substrate is connected to a printed circuit board wherein thermal pathways are formed 1) from the die downward to the substrate to the printed circuit board and 2) from the die upward to the re-routable clip and then downward through the leads to the substrate and to the printed circuit board.Type: ApplicationFiled: February 19, 2018Publication date: August 22, 2019Inventors: Tung Ching Lui, Baltazar Canete, Melvin Martin, Rajesh Subraya Aiyandra
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Publication number: 20190229028Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.Type: ApplicationFiled: January 25, 2018Publication date: July 25, 2019Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Publication number: 20190096815Abstract: A system in package is provided comprising an embedded trace substrate having redistribution layers therein, at least one passive component mounted on one side of the embedded trace substrate and embedded in a first molding compound, at least one silicon die mounted on an opposite side of the embedded trace substrate and embedded in a second molding compound wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers, and solder balls mounted through openings in the second molding layer to the redistribution layers wherein the solder balls provide package output.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: Jesus Mennen Belonio, JR., Shou Cheng Eric Hu, Ian Kent, Ernesto Gutierrez, III, Melvin Martin, Rajesh Subraya Aiyandra
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Publication number: 20190067229Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Inventors: Habeeb Mohiuddin Mohammed, Rajesh Subraya Aiyandra
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Patent number: 10083926Abstract: A wafer level chip scale package is described. At least one redistribution layer is connected to a wafer through an opening through a first polymer layer to a metal pad on a top surface of the wafer wherein the redistribution layer has a roughened top surface and wherein holes are formed through the at least one redistribution layer in an area where the redistribution layer has an area exceeding 0.2 mm2. At least one UBM layer contacts the at least one redistribution layer through an opening in a second polymer layer wherein the second polymer layer contacts the first polymer layer within the holes promoting cohesion between the first and second polymer layers and wherein the roughened top surface promotes adhesion between the at least one redistribution layer and the second polymer layer.Type: GrantFiled: December 13, 2017Date of Patent: September 25, 2018Assignee: Dialog Semiconductor (UK) LimitedInventors: Ian Kent, Rajesh Subraya Aiyandra, Jesus Mennen Belonio, Jr., Habeeb Mohiuddin Mohammed, Domingo Jr. Maggay, Robert Lamoon, Ernesto Gutierrez, III
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Publication number: 20180025965Abstract: A quad flat no lead package is provided comprising at least one first integrated circuit die embedded in a recess in a die paddle of a metal leadframe and a second integrated circuit chip die attached to the at least one first integrated circuit die wherein the first and second integrated circuit dies are electrically connected to each other and wherein the second integrated circuit die is connected to leads of the leadframe through copper pillars.Type: ApplicationFiled: July 19, 2016Publication date: January 25, 2018Inventors: Baltazar Canete, JR., Melvin Martin, Ian Kent, Jesus Mennen Belonio, JR., Rajesh Subraya Aiyandra