Patents by Inventor Rajesh Verma
Rajesh Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153487Abstract: Data indicative of one or more user inputs directed to a user interface of a conversation designer tool is received. A conversation design is determined based on the data. The conversation design enables a conversation bot to provide a service using a conversation flow specified at least in part by the conversation design. The conversation design specifies in a first human language at least a portion of a message content to be provided by the conversation bot during an execution of the conversation flow. It is identified that an end-user of the conversation bot prefers to converse in a second human language different from the first human language. The message content of the conversation design in the first human language is dynamically translated for the end-user to the second human language.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Inventors: Jebakumar Mathuram Santhosm Swvigaradoss, Satya Sarika Sunkara, Ankit Goel, Rajesh Voleti, Rishabh Verma, Patrick Casey, Rao Surapaneni
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Patent number: 11947504Abstract: In some implementations, a device may receive a request to merge a first cloud computing instance with a second cloud computing instance to generate a multi-cloud computing instance. The device may access a first application programming interface to obtain a first configuration of the first cloud computing instance. The device may access a second application programming interface to obtain a second configuration of the second cloud computing instance. The device may generate a target configuration based on the first configuration or the second configuration. The device may instantiate a set of resources with the target configuration for the multi-cloud computing instance. The device may provide output identifying the multi-cloud computing instance.Type: GrantFiled: October 31, 2022Date of Patent: April 2, 2024Assignee: Accenture Global Solutions LimitedInventors: Vaibhav Mahendrabhai Shah, Nikhil Prakash Bhandari, Ankit Gupta, Rashika Dayaram Choudhari, Anu Saxena, Hirendra Parihar, Kushal Verma, Lalitkumar Maganlal Jain, Himanshu Nityanand Puranik, Rajesh Bhat
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Publication number: 20230088328Abstract: The present disclosure generally relates to a system for crime risk forecasting using cyber security and deep learning comprises a data input unit for receiving a pre-stored crime event dataset and real time crime event data input along with geographical details of an area; a classification processing unit for categorizing pre-stored crime event dataset and real time crime event data input according to crime type; a graphical user interface for entering a target geographic area for forecasting upcoming crime risk; a central processing unit for generating a crime risk forecast based on the historical crime incident stored in the pre-stored crime event dataset using a deep leaning technique; and a control unit coupled to a display for displaying a crime risk ranking generated based on the crime risk forecast and one or more crime risk event for the target geographic area.Type: ApplicationFiled: November 23, 2022Publication date: March 23, 2023Inventors: Abdulwasa Bakr Barnawi, Neeraj Kumar Shukla, Vineet Tirth, Javed Khan Bhutto, M. Ramkumar Raja, Rajesh Verma, Samidha Dwivedi Sharma, Vivek Kumar, Pawan Kumar Singh, B.K. Sarkar
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Patent number: 10394299Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.Type: GrantFiled: May 23, 2016Date of Patent: August 27, 2019Assignee: QUALCOMM IncorporatedInventors: Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
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Patent number: 9958918Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.Type: GrantFiled: May 23, 2016Date of Patent: May 1, 2018Assignee: QUALCOMM IncorporatedInventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
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Publication number: 20170336845Abstract: A system includes a processing core built on a semiconductor substrate, the processing core having a first sub core and a second sub core, each of the first and second sub cores configured to perform a processing function, and a plurality of power rails traversing a dimension of the processing core and spanning from the first sub core to the second sub core, each of the power rails being configured to provide an operating voltage to the first and second sub cores, and wherein a boundary between the first sub core and the second sub core is irregularly shaped, and wherein each of the first and second sub cores corresponds to a respective power domain.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Inventors: Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
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Publication number: 20170336840Abstract: A semiconductor device includes: a processing core having a plurality of sub cores, a plurality of power rails spanning from a first sub core to a second sub core of the plurality of sub cores, the plurality of power rails configured to provide an operating voltage to each of the first sub core and the second sub core, and a plurality of cells defining a boundary between the first sub core and the second sub core, each of the cells providing a discontinuity in a respective power rail, wherein the discontinuity includes a break in the respective power rail in more than one layer of the semiconductor device.Type: ApplicationFiled: May 23, 2016Publication date: November 23, 2017Inventors: Satyanarayana Sahu, Satish Raj, Shiva Ram Chandrasekaran, Li Qiu, Arun Tyagi, Mathew Philip, Rajesh Verma
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Patent number: 9190358Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: GrantFiled: September 12, 2014Date of Patent: November 17, 2015Assignee: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Publication number: 20150320340Abstract: A method for preventing a viral related infection includes obtaining a sample from a person, assaying the sample to determine whether the person has been previously infected with a virus, and if the person has not been previously infected, providing the person with at least one sensor positioned to detect when a person's hand approaches a predetermined position related to the ground or their own body. By warning the person of undesired hand-to- face contacts, the person is able to reduce the incidence of viral related infections.Type: ApplicationFiled: February 20, 2015Publication date: November 12, 2015Inventor: Rajesh Verma
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Publication number: 20140374873Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: ApplicationFiled: September 12, 2014Publication date: December 25, 2014Inventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Patent number: 8853815Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: GrantFiled: March 14, 2013Date of Patent: October 7, 2014Assignee: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Publication number: 20140264715Abstract: A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Sundararajan Ranganathan, Paras Gupta, Raghavendra Dasegowda, Rajesh Verma, Parissa Najdesamii
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Patent number: 5904842Abstract: Debris removing screen basket and overflow apparatus embodiments for use in a storm collection sewer. The device has two embodiments, each including a central panel with foldable wings in each side of the central panel. During initial assembly, the wings are folded up around the central panel for insertion through a manhole cover. Each wing can have an optional extension panel. In the first embodiment, the wings, extension panels and the central panel form a single type panel that is inclined at a variable angle so as to suit various floor conditions at a particular location. Both wings and extension panels have angled deflector top portions, while the central panel does not. A screen mesh basket is supported behind the central panel. Storm water and debris fill up the area in front of the apparatus. The rising water when reaching the height of the deflector portions is forced over the central panel and into the basket.Type: GrantFiled: October 18, 1996Date of Patent: May 18, 1999Inventors: Charles Billias, Rajesh Verma, Ray Waton
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Patent number: 5643445Abstract: Debris removing screen basket and overflow apparatus embodiments for use in a storm collection sewer. The device has two embodiments, each including a central panel with foldable wings in each side of the central panel. During initial assembly, the wings are folded up around the central panel for insertion through a manhole cover. Each wing can have an optional extension panel that slidable attached to each wing by bolts/screws and nuts through longitudinal slots. In the first embodiment, the wings, extension panels and the central panel form a single type panel that is inclined at a variable angle so as to suit various floor conditions at a particular location. In the first embodiment the panel and wings have a front edge that sits on the inlet drain floor and a top edge touching an upper ridge of the basket.Type: GrantFiled: August 28, 1995Date of Patent: July 1, 1997Inventors: Charles Billias, Rajesh Verma, Ray Waton