Patents by Inventor Rajesh Vivekanandham

Rajesh Vivekanandham has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12294368
    Abstract: The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.
    Type: Grant
    Filed: September 24, 2021
    Date of Patent: May 6, 2025
    Assignee: Intel Corporation
    Inventors: Rahul Pal, Dheeraj Subbareddy, Mahesh Kumashikar, Dheemanth Nagaraj, Rajesh Vivekanandham, Anshuman Thakur, Ankireddy Nalamalpu, Md Altaf Hossain, Atul Maheshwari
  • Publication number: 20220222194
    Abstract: Methods and apparatus for on-package accelerator complex (AC) for integrating accelerator and IOs for scalable RAN and edge cloud solutions. The AC comprises one or more dies including an IO interface tile that is coupled to multiple intellectual property (IP) blocks that may be integrated on the same die as the IO interface tile or separate dies that are coupled to the IO interface tile via die-to-die or chiplet-to-chiplet interconnects. The IP blocks may include a network interface (e.g., Ethernet) and one or more accelerators. The package further includes a central processing unit (CPU) that is coupled to the AC via a die-to-die or chiplet-to-chiplet interconnect. The IO interface tile includes integrated shared scratchpad memory that is shared among the IP blocks and the CPU cores. The IO interface tile further includes an interface controller for scheduling IP blocks and configuring data transfers between the IP blocks, such as used by a RAN pipeline.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Neelam CHANDWANI, Shridhar BENDI, Rajesh VIVEKANANDHAM, Rahul PAL, Eric J. DAHLEN, Antonio J. HASBUN MARIN, Chung-Chi WANG, Qian LI, Hosein NIKOPOUR, Sravanthi KOTA VENKATA, Rajesh POORNACHANDRAN, Udayan MUKHERJEE
  • Publication number: 20220044123
    Abstract: Processors may be enhanced by embedding programmable logic devices, such as field-programmable gate arrays. For instance, an application-specific integrated circuit device may include main fixed function circuitry operable to perform a main fixed function of the application-specific integrated circuit device. The application-specific integrated circuit also includes a support processor that performs operations outside of the main fixed function of the application-specific integrated circuit device, wherein the support processor comprises an embedded programmable fabric to provide programmable flexibility to application-specific integrated circuit device.
    Type: Application
    Filed: September 24, 2021
    Publication date: February 10, 2022
    Inventors: Rajesh Vivekanandham, Dheeraj Subbareddy, Dheemanth Nagaraj, Vijay S. R. Degalahal, Anshuman Thakur, Ankireddy Nalamalpu, MD Altaf Hossain, Mahesh Kumashikar, Atul Maheshwari
  • Publication number: 20220014202
    Abstract: The present disclosure is directed to 3-D stacked architecture for Programmable Fabrics and Central Processing Units (CPUs). The 3-D stacked orientation enables reconfigurability of the fabric, and allows the fabric to function using coarse-grained and fine-grained acceleration for offloading CPU processing. Additionally, the programmable fabric may be able to function to interface with multiple other compute chiplet components in the 3-D stacked orientation. This enables multiple compute components to communicate without the need for offloading the data communications between the compute chiplets.
    Type: Application
    Filed: September 24, 2021
    Publication date: January 13, 2022
    Inventors: Rahul Pal, Dheeraj Subbareddy, Mahesh Kumashikar, Dheemanth Nagaraj, Rajesh Vivekanandham, Anshuman Thakur, Ankireddy Nalamalpu, MD Altaf Hossain, Atul Maheshwari