Patents by Inventor Rajesh Vridhachalam

Rajesh Vridhachalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10102524
    Abstract: An illustrative apparatus includes a memory, a processor coupled to the memory, and a first set of instructions stored on the memory that can be executed by the processor. The processor is configured to determine authentication data, where the authentication data comprises an indication that a first functionality of a second set of instructions can be controlled and where the second set of instructions is separate from the first set of instructions. The processor is further configured to send to a user interface, an indication of the first functionality. The processor is further configured to receive, through the user interface, a request to control the first functionality of a second set of instructions that is separate from the first set of instructions. The processor is further configured to send an order to control the first functionality of the second set of instructions.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: October 16, 2018
    Assignee: U.S. BANCORP, NATIONAL ASSOCIATION
    Inventors: Rajesh Vridhachalam, Jason A. Witty
  • Publication number: 20170352028
    Abstract: An illustrative apparatus includes a memory, a processor coupled to the memory, and a first set of instructions stored on the memory that can be executed by the processor. The processor is configured to determine authentication data, where the authentication data comprises an indication that a first functionality of a second set of instructions can be controlled and where the second set of instructions is separate from the first set of instructions. The processor is further configured to send to a user interface, an indication of the first functionality. The processor is further configured to receive, through the user interface, a request to control the first functionality of a second set of instructions that is separate from the first set of instructions. The processor is further configured to send an order to control the first functionality of the second set of instructions.
    Type: Application
    Filed: June 3, 2016
    Publication date: December 7, 2017
    Inventors: Rajesh Vridhachalam, Jason A. Witty