Patents by Inventor Rajeswaran CHOCKALINGAPURAMRAVINDRAN

Rajeswaran CHOCKALINGAPURAMRAVINDRAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240070812
    Abstract: A processor-implemented method comprises processing a single level cost volume across multiple processing stages by varying a receptive field across each of the processing stages. The method also includes performing a learning-based correspondence estimation task based on the processing. The varying may include processing a different resolution of the cost volume at each processing stage while maintaining a same neighborhood sampling radius. The resolution may increase from a first processing stage to a later processing stage. The varying may also include varying a neighborhood sampling radius at each of the processing stages while maintaining a same resolution. The task may be optical flow estimation or stereo estimation.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 29, 2024
    Inventors: Risheek GARREPALLI, Rajeswaran CHOCKALINGAPURAMRAVINDRAN, Jisoo JEONG, Fatih Murat PORIKLI
  • Publication number: 20230186487
    Abstract: A computer-implemented method includes receiving a first input. The first input is interpolated based on a first shift along a first dimension and a second shift along a second dimension. A first output is generated based on the interpolated first input. The first output corresponds to a vectorized bilinear shift of the first input for use in place of grid sampling algorithms.
    Type: Application
    Filed: December 13, 2021
    Publication date: June 15, 2023
    Inventors: Rajeswaran CHOCKALINGAPURAMRAVINDRAN, Kristopher URQUHART, Jamie Menjay LIN, Risheek GARREPALLI
  • Publication number: 20220108165
    Abstract: A method for operating an artificial neural network (ANN) includes quantifying a reward for executing ANN tasks in a system having multiple processing cores. A set of processing cores of the multiple processing cores is allocated to execute each of the tasks based on the reward. The ANN tasks are executed concurrently according to the processing core allocation to operate the ANN.
    Type: Application
    Filed: October 2, 2020
    Publication date: April 7, 2022
    Inventor: Rajeswaran CHOCKALINGAPURAMRAVINDRAN