Abstract: A method for high speed searching of a large database provides speed, throughput, and efficient memory usage comparable to TCAM-assisted searches without using dedicated processors. Successive groups of bits from a key are processed by tables in a search tree. The tables are constructed with different sizes and types according to the structure of the key and the distribution of information in the database. Each link to a subsequent table specifies both the type of the linked table and how many key bits the table will process. The tables include, but are need not be limited to, address offset tables that use bits from the key as an addressing offset to locate a result. Embodiments are implemented on pipeline processors that include internal memory units and access to external memory. Embodiments also include string compare tables, memory mapped tables, and/or instructions to continue searching on a different memory unit.

Abstract: An improved data networking technique and apparatus using a novel physically distributed but logically shared and data-sliced synchronized shared memory switching datapath architecture integrated with a novel distributed data control path architecture to provide ideal output-buffered switching of data in networking systems, such as routers and switches, to support the increasing port densities and line rates with maximized network utilization and with per flow bit-rate latency and jitter guarantees, all while maintaining optimal throughput and quality of services under all data traffic scenarios, and with features of scalability in terms of number of data queues, ports and line rates, particularly for requirements ranging from network edge routers to the core of the network, thereby to eliminate both the need for the complication of centralized control for gathering system-wide information and for processing the same for egress traffic management functions and the need for a centralized scheduler, and elimina

Abstract: A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.