Patents by Inventor Rajinder Sandhu

Rajinder Sandhu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8575657
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Grant
    Filed: March 20, 2012
    Date of Patent: November 5, 2013
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20130248879
    Abstract: A GaN high electron mobility transistor (HEMT) device having a silicon carbide substrate including a top surface and a bottom surface, where the substrate further includes a via formed through the bottom surface and into the substrate. The device includes a plurality of epitaxial layers provided on the top surface of the substrate, a plurality of device layers provided on the epitaxial layers, and a diamond layer provided within the via.
    Type: Application
    Filed: March 20, 2012
    Publication date: September 26, 2013
    Applicant: Northrop Grumman Systems Corporation
    Inventors: Vincent Gambin, Rajinder Sandhu, Benjamin Poust, Michael Wojtowicz
  • Publication number: 20090045437
    Abstract: The disclosure relates to a method for forming an intermediate lattice transition buffer layer. The method includes: (a) depositing a first graded InAlAs layer on a substrate at a first constant temperature, the first graded InAlAs layer having an In/AI composition ratio which increases across the buffer layer from a first level to a second level; (b) annealing at least the first graded InAlAs layer; (c) depositing the second graded InAlAs layer on the first graded InAlAs layer at the first constant temperature, the second graded InAlAs layer having an In/Al composition ratio which increases across the buffer layer from the second level to a third level; and (d) annealing at least the second graded InAlAs layer; the buffer layer being formed under Groups III/V overpressure.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 19, 2009
    Applicant: Northrop Grumman Space & Mission Systems Corp.
    Inventors: Rajinder Sandhu, Abdullah Cavus, Cedric Monier, Augusto Gutierrez
  • Publication number: 20070215280
    Abstract: A semiconductor surface processing method in one example comprises disposing a polishing pad in rotating engagement with a semiconductor wafer to be polished, dripping a first polishing solution onto the polishing pad at a first drip rate, and, concurrently, dripping a second polishing solution onto the polishing pad at a second drip rate.
    Type: Application
    Filed: March 15, 2006
    Publication date: September 20, 2007
    Inventors: Rajinder Sandhu, Roosevelt Johnson, Cedric Monier, Augusto Gutierrez-Aitken
  • Publication number: 20070218611
    Abstract: An improved HEMT formed from a GaN material system is disclosed which has reduced gate leakage current relative to known GaN based HEMTs and eliminates the problem of current constrictions resulting from deposition of the gate metal over the step discontinuities formed over the gate mesa. The HEMT device is formed from a GaN material system. One or more GaN based materials are layered and etched to form a gate mesa with step discontinuities defining source and drain regions. In order to reduce the leakage current, the step discontinuities are back-filled with an insulating material, such as silicon nitride (SiN), forming a flat surface relative to the source and drain regions, to enable to the gate metal to lay flat. By back-filling the source and drain regions with an insulating material, leakage currents between the gate and source and the gate and drain are greatly reduced. In addition, current constrictions resulting from the deposition of the gate metal over a step discontinuity are virtually eliminated.
    Type: Application
    Filed: March 14, 2006
    Publication date: September 20, 2007
    Inventors: Rajinder Sandhu, Michael Barsky, Michael Wojtowicz
  • Publication number: 20050090076
    Abstract: Die of high aspect ratio formed in a hard wafer substrate are sawed out without requiring tape, obtaining high die yields. Preliminary to sawing the semiconductor die (3) from a sapphire wafer (2), the wafer is joined (20) to a silicon carrier substrate (6) by a thermoplastic layer (4) forming a unitary sandwich-like assembly. Sawing the die from the wafer follows. The thermoplastic is removed, and the die may be removed individually (50) from the silicon carrier substrate. Thermoplastic produces a bond that holds the die in place against the shear force exerted by the saw and by the stream of coolant (30).
    Type: Application
    Filed: October 22, 2003
    Publication date: April 28, 2005
    Inventors: Michael Barsky, Michael Wojtowicz, Rajinder Sandhu