Patents by Inventor Rajith Mavila
Rajith Mavila has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230349970Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: ApplicationFiled: July 6, 2023Publication date: November 2, 2023Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 11726139Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: GrantFiled: August 8, 2022Date of Patent: August 15, 2023Assignee: NVIDIA CorporationInventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Publication number: 20220382659Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 11408934Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: GrantFiled: December 21, 2018Date of Patent: August 9, 2022Assignee: Nvidia CorporationInventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 11294441Abstract: In various embodiments, rail decoupling circuits that are powered by an always on voltage rail allow a core voltage rail to power up independently of an I/O voltage rail without jeopardizing I/O pad circuits that are powered by the I/O voltage rail. In an embodiment, when the always on voltage rail is powered-up and a chip reset signal is asserted, the rail decoupling circuits drive control inputs of the I/O pad circuits based on default values. When the chip reset signal is de-asserted, the rail decoupling circuits drive the control inputs of the I/O pad circuits based on signals received from circuits powered by the core voltage rail. Because the rail decoupling circuits maintain control of the I/O pad circuits until the chip-reset is de-asserted, the core voltage rail can power up at any time before the chip-reset signal is de-asserted irrespective of when the I/O voltage rail powers up.Type: GrantFiled: June 25, 2020Date of Patent: April 5, 2022Assignee: NVIDIA CORPORATIONInventors: Rajith Mavila, Venkata Suresh Perumalla, Kwok San Lee
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Publication number: 20210405719Abstract: In various embodiments, rail decoupling circuits that are powered by an always on voltage rail allow a core voltage rail to power up independently of an I/O voltage rail without jeopardizing I/O pad circuits that are powered by the I/O voltage rail. In an embodiment, when the always on voltage rail is powered-up and a chip reset signal is asserted, the rail decoupling circuits drive control inputs of the I/O pad circuits based on default values. When the chip reset signal is de-asserted, the rail decoupling circuits drive the control inputs of the I/O pad circuits based on signals received from circuits powered by the core voltage rail. Because the rail decoupling circuits maintain control of the I/O pad circuits until the chip-reset is de-asserted, the core voltage rail can power up at any time before the chip-reset signal is de-asserted irrespective of when the I/O voltage rail powers up.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Rajith MAVILA, Venkata Suresh PERUMALLA, Kwok San LEE
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Publication number: 20190195947Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: ApplicationFiled: December 21, 2018Publication date: June 27, 2019Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 7603575Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.Type: GrantFiled: June 30, 2005Date of Patent: October 13, 2009Inventors: Nancy G. Woodbridge, Mark N. Fullerton, Amit Dor, Vasudev Bibikar, Rajith Mavila
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Publication number: 20070006007Abstract: An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Nancy Woodbridge, Mark Fullerton, Amit Dor, Vasudev Bibikar, Rajith Mavila
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Publication number: 20060200684Abstract: A computerized system includes at least one digital logic circuit and a power control circuit. The power control circuit is operable to reduce the voltage of a power signal applied to the at least one digital logic circuit, operable to bring the digital logic circuit from a high power level to a low power level, and operable to increase the voltage of the power signal applied to the digital logic circuit before bringing the digital logic circuit from a low power level to a high power level.Type: ApplicationFiled: March 1, 2005Publication date: September 7, 2006Inventors: Vasudev Bibikar, Rajith Mavila