Patents by Inventor Rajiv Dunne

Rajiv Dunne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090289648
    Abstract: Various exemplary embodiments provide probes, systems and methods for measuring an effective electrical resistance/resistivity with high sensitivity. In one embodiment, the measuring system can include an upper probe set and a similar lower probe set having a sample device sandwiched there-between. The device-under-test (DUT) samples can be sandwiched between two conductors of the sample device. Each probe set can have an inner voltage sense probe coaxially configured inside an electrically-isolated outer current source probe that has a large contact area with the sample device. The measuring system can also include a computer readable medium for storing circuit simulations including such as FEM simulations for extracting a bulk through-plane electrical resistivity and an interface resistivity for an effective electrical z-resistivity of the DUT, in some cases, having sub-micro-ohm resistance.
    Type: Application
    Filed: May 22, 2009
    Publication date: November 26, 2009
    Inventors: Michael Anthony Lamson, Siva Prakash Gurrum, Rajiv Dunne
  • Publication number: 20070004083
    Abstract: In a semiconductor flip-chip package having a semiconductor die as part of a substrate assembly, a lid (or lid assembly) and substrate are supported to prevent tilting and teetering of the lid. The lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. An adhesion prohibitor may be applied so that a support does not adhere to both lid and substrate; the support may be prevented from adhering to both lid and substrate by a separate curing step. The arrangements and fabrication methods may be applied to many package types, including ball grid array (BGA) and land grid array (LGA) packages.
    Type: Application
    Filed: September 6, 2006
    Publication date: January 4, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Tz-Cheng Chiu, Rajiv Dunne
  • Publication number: 20060027921
    Abstract: In a semiconductor flip-chip package having a semiconductor die 104 as part of a substrate assembly, a lid 110 (or lid assembly) and substrate 102 are supported with respect to each other so as to prevent tilting and teetering of the lid during socketing, testing, application of heat sinks, and so forth. Yet the lid and substrate do not adhere, so as to reduce cracking of solder joints due to thermal cycling induced by repeated system power on-off. In some embodiments, an adhesion prohibitor 315, 325 may be explicitly applied so that a support 314, 324 does not adhere to both lid and substrate; in other embodiments, the support 314, 324 may be prevented from adhering to both lid and substrate by a separate curing step. That is, fabrication methods (FIGS. 4A, 4B) involving an adhesive prohibitor may involve a single curing step for the support material and a lid-attach adhesive 112 (such as a polymer), while fabrication methods (FIGS.
    Type: Application
    Filed: August 7, 2004
    Publication date: February 9, 2006
    Inventors: Tz-Cheng Chiu, Rajiv Dunne