Abstract: A flexible tile-based place-and-route methodology utilizes pre-generated physical layer (PHY) tiles to greatly simplify the task of automatically generating routing solutions between associated PHYs disposed on a memory device and a corresponding processor for any selected floorplan positioning of the memory device relative to the corresponding processor. The PHY tiles are pre-generated software-based layout descriptions that model the densely-packed 2D contact PHY pad arrays, and also comprise partial layout features including signal line segments that escape routing pins from the 2D contact pads to an orthogonal (straight-line) edge of the PHY tile and disposed in design-rule-compliant spaced-apart arrangements. Optional 45-degree jog line segments are utilized to efficiently correct for alignment offsets between the memory PHY and processor PHY.

Abstract: A flexible tile-based place-and-route methodology utilizes pre-generated physical layer (PHY) tiles to greatly simplify the task of automatically generating routing solutions between associated PHYs disposed on a memory device and a corresponding processor for any selected floorplan positioning of the memory device relative to the corresponding processor. The PHY tiles are pre-generated software-based layout descriptions that model the densely-packed 2D contact PHY pad arrays, and also comprise partial layout features including signal line segments that escape routing pins from the 2D contact pads to an orthogonal (straight-line) edge of the PHY tile and disposed in design-rule-compliant spaced-apart arrangements. Optional 45-degree jog line segments are utilized to efficiently correct for alignment offsets between the memory PHY and processor PHY.