Abstract: A method, computer program product, and apparatus for efficiently utilizing software licenses in a large organization having multiple divisions is disclosed. A preferred embodiment of the present invention accomplishes this goal by providing for a pool of organization-wide software licenses. This license pool is subdivided into a number of reserved or dedicated licenses for each particular division and a set of shared licenses to be shared among the various divisions. A given division, when checking out licenses from the organization-wide pool, will first exhaust its reserved licenses before checking out shared licenses. In the event that all shared licenses are being used, but there are reserved licenses that are sitting idle, a division may borrow a reserved license from another division, subject to the lending division's right of preemption in the event that the borrowed license is needed by the division lending the license.

Abstract: A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.

Abstract: A method for synchronizing clock pulses for an integrated circuit includes the steps of (a) finding a relative delay with respect to a clock signal for a plurality of circuit elements and (b) inserting a delay cell between the clock signal and each of the plurality of circuit elements for each of the plurality of circuit elements wherein the delay cell has a relative delay greater than a minimum delay to minimize clock skew.

Abstract: A method of clock buffer placement for minimizing clock skew for an integrated circuit includes the steps of (a) finding an ideal location for a clock buffer on an integrated circuit that minimizes clock skew, (b) checking whether the ideal clock buffer location overlaps a megacell, and (c) finding a location for the clock buffer that is closest to the ideal clock buffer location and that does not overlap a megacell.

Abstract: Methods for using the polysilicon layer to route the cells in the ASIC are disclosed. The poly layer of an IC chip is used for routing chip interconnects with minimal impact on the chip performance by selecting nets in the IC chip based on a predetermined or a desired qualification. A maximum allowable length of the poly layer to be used for chip interconnects is determined based on the intended technology of the chip. A filtering algorithm filters the netlist to provide a set of candidate nets that are suitable for poly layer routing based on the predetermined or desired qualification. A routing tool routes the selected nets that have been selected by the filtering algorithm by using the poly layer. Some of the poly layer routings are further rejected by a post processing step.