Patents by Inventor Rajiv Kumar Sisodia
Rajiv Kumar Sisodia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11900995Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: GrantFiled: April 6, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Patent number: 11901290Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.Type: GrantFiled: January 14, 2021Date of Patent: February 13, 2024Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen
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Patent number: 11830542Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.Type: GrantFiled: August 29, 2022Date of Patent: November 28, 2023Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Disha Singh, Gautam Garg, Srinivasan Srinath, Georgy Jacob
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Patent number: 11676656Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.Type: GrantFiled: February 5, 2021Date of Patent: June 13, 2023Assignee: Arm LimitedInventors: Andy Wangkun Chen, Yew Keong Chong, Rajiv Kumar Sisodia, Sriram Thyagarajan
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Publication number: 20230136348Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.Type: ApplicationFiled: October 29, 2021Publication date: May 4, 2023Inventors: Sriram Thyagarajan, Yew Keong Chong, Munish Kumar, Andy Wangkun Chen, Rajiv Kumar Sisodia
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Patent number: 11631439Abstract: Various implementations described herein are directed to a device having memory control circuitry having global passgates and a read-write driver that provides a global read-write signal to the global passgates. The device may have sense amplifier circuitry with local-drivers and a sense amplifier driver that provides a sense amplifier enable signal to the local-drivers, wherein the local-drivers may include multiple buffers coupled to the sense amplifier driver in parallel.Type: GrantFiled: October 29, 2021Date of Patent: April 18, 2023Assignee: Arm LimitedInventors: Sriram Thyagarajan, Yew Keong Chong, Munish Kumar, Andy Wangkun Chen, Rajiv Kumar Sisodia
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Publication number: 20220415385Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.Type: ApplicationFiled: August 29, 2022Publication date: December 29, 2022Inventors: Rajiv Kumar Sisodia, Disha Singh, Gautam Garg, Srinivasan Srinath, Georgy Jacob
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Patent number: 11514979Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.Type: GrantFiled: March 31, 2021Date of Patent: November 29, 2022Assignee: Arm LimitedInventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, Jr.
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Publication number: 20220319586Abstract: Various implementations described herein are related to a method for accessing a bitcell in an array of bitcells with a wordline and a bitline. The method may perform a precharge operation on the bitline that precharges the bitline after a read cycle and before a write cycle. Also, the method may extend precharge time of the precharge operation between the read cycle and the write cycle, e.g., by modulating a wordline signal on the wordline with early cut-off of the wordline signal on the wordline during the read cycle.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Sriram Thyagarajan, Yew Keong Chong, Ayush Kulshrestha, Munish Kumar
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Publication number: 20220319585Abstract: Various implementations described herein are related to a device with a wordline driver that provides a wordline signal to a wordline based on a row selection signal and a row clock signal. The device may have row selector logic that provides the row selection signal to the wordline driver based on first input signals in a periphery voltage domain. The device may also have level shifter circuitry that provides the row clock signal to the wordline driver in a core voltage domain based on second input signals in the periphery voltage domain.Type: ApplicationFiled: March 31, 2021Publication date: October 6, 2022Inventors: Andy Wangkun Chen, Munish Kumar, Ayush Kulshrestha, Rajiv Kumar Sisodia, Yew Keong Chong, Kumaraswamy Ramanathan, Edward Martin McCombs, JR.
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Patent number: 11430506Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.Type: GrantFiled: February 10, 2020Date of Patent: August 30, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Disha Singh, Gautam Garg, Srinivasan Srinath, Georgy Jacob
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Publication number: 20220254411Abstract: Various implementations described herein are related to a device having memory circuitry with bitlines coupled to an array of bitcells. Also, the device may have first precharge circuitry that precharges the bitlines before a write cycle. Also, the device may have second precharge circuitry that precharges the bitlines after the write cycle.Type: ApplicationFiled: February 5, 2021Publication date: August 11, 2022Inventors: Andy Wangkun Chen, Yew Keong Chong, Rajiv Kumar Sisodia, Sriram Thyagarajan
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Publication number: 20220223514Abstract: Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.Type: ApplicationFiled: January 14, 2021Publication date: July 14, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen
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Patent number: 11322197Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: GrantFiled: October 21, 2020Date of Patent: May 3, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
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Patent number: 11315628Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.Type: GrantFiled: October 21, 2020Date of Patent: April 26, 2022Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony
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Publication number: 20220123751Abstract: Various implementations described herein are related to a device having logic that operates in multiple voltage domains. The device may include a backside power network with rows of segmented supply rails coupled to the logic. The rows of segmented supply rails may include alternating rail breaks that define an interchanging directional supply of power to the logic in the multiple voltage domains.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Sriram Thyagarajan, Yew Keong Chong, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Rajiv Kumar Sisodia
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Publication number: 20220122656Abstract: Various implementations described herein are related to a device having wordline drivers coupled to a core array. The device may have backside power network with buried power rails. The device may have header logic coupled to power supply connections of the wordline drivers by way of the buried power rails, and the header logic may be used to power-gate the wordline drivers.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony, Sriram Thyagarajan, Yew Keong Chong
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Publication number: 20220122654Abstract: Various implementations described herein are directed to a device having memory with a first array and a second array. The device may have power rails formed in frontside metal layers that supply core voltage to the memory. The power rails may include a first path routed through a first frontside metal layer to the first array of the memory, and the power rails may include a second path routed through the first frontside metal layer and a second frontside metal layer to the second array of the memory.Type: ApplicationFiled: October 21, 2020Publication date: April 21, 2022Inventors: Rajiv Kumar Sisodia, Andy Wangkun Chen, Ayush Kulshrestha, Sony
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Patent number: 11100965Abstract: Various implementations described herein are related to a device having an array of bitcells that are accessible via wordlines and bitlines including unselected bitlines and a selected bitline. Each bitcell in the array of bitcells may be selectable via a selected wordline of the wordlines and the selected bitline of the bitlines. The device may include precharge circuitry that is configured to selectively precharge the unselected bitlines and the selected bitline before arrival of a wordline signal on the selected wordline.Type: GrantFiled: March 17, 2020Date of Patent: August 24, 2021Assignee: Arm LimitedInventors: Rajiv Kumar Sisodia, Disha Singh, Yattapu Viswanatha Reddy
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Publication number: 20210249070Abstract: Various implementations described herein are directed to a device having a first read wordline formed in a first metal layer and a read wordline driver having an output node coupled to one or more memory cells via the first read wordline formed in the first metal layer. The device may include a second read wordline formed in a second metal layer that is different than the first metal layer, and the read wordline driver may have an input node coupled to the second read wordline formed in the second metal layer.Type: ApplicationFiled: February 10, 2020Publication date: August 12, 2021Inventors: Rajiv Kumar Sisodia, Disha Singh, Gautam Garg, Srinivasan Srinath, Georgy Jacob
