Abstract: A system that generates a visualization user interface. The system receives a selection of a data source, and receives a selection of a visualization template that includes metadata. The system further receives a selection of data attributes corresponding to the data source. The system parses the visualization template for the metadata, and replaces the metadata with binding between a visualization component and the data source. The system then generates the visualization user interface using the visualization component.

Abstract: Polypyrrole/carbon (PPy/C) composite doped with organic anion p-toluenesulfonate (pTS) is utilized as an electrode in supercapacitor for energy storage application. The surface initiated in-situ chemical oxidative polymerization yields a composite material PPy/C in the presence of varying concentrations of pTS. The novelty of the present invention lies in the doping of PPy/C composite with organic anion pTS and consequent enhancement of its electrochemical activity and stability. The conjugation length and electrical conductivity of pTS doped PPy/C composites increase with the increase in dopant concentration. The pTS doped PPy/C composite synthesized using equimolar concentration (0.1 M) of pTS to pyrrole shows the maximum specific capacitance of ˜395 F/g in 0.5 M Na2SO4 aqueous solution with significant stability ˜95% capacitance retention after ˜500 cycles.

Abstract: An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.

Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Abstract: Single-ended read circuits for SRAM devices are disclosed for high performance sub-micron designs. One embodiment is an SRAM device that includes a memory cell array and a bit line traversing the memory cell array for reading data from memory cells of the memory cell array. A read circuit coupled to the bit line translates data stored in a memory cell from a cell voltage of the memory cells to a peripheral voltage of an output of the SRAM device while bypassing a level shifter in the read data path.

Abstract: Word line decoders for dual rail SRAM devices are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a word line traversing the memory cell array for selecting memory cells of the memory cell array. A row decode-driver coupled to the word line toggles the word line between logic levels of a memory cell supply based on select signals that toggle between logic levels of a peripheral supply. The row decoder-driver toggles the word line without utilizing level shifters along the word line access path.

Abstract: A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test.

Abstract: A system and method enabling automated data cleansing and scrubbing at the attribute level is disclosed. A consolidated view may be provided of the scrubbed data or narratives that gets promoted to a final copy and the data or narratives received from multiple sources on a single user interface.

Abstract: A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.

Abstract: A method of determining at least one point of entry of smoke into a smoke detection system, the system having a sampling pipe network including at least one sampling pipe and a plurality of sampling inlets through which an air sample can enter the at least one sampling pipe of the smoke detection system for analysis by a particle detector, said method including: determining a volume of sample air that has passed through at least part of the smoke detection system since a predetermined event or a value corresponding to said volume; and determining through which sampling inlet of the plurality of sampling inlets the smoke entered the smoke detection system based, at least in part, on the determined volume or value. Systems for implementing such a method and related methods are also described.

Abstract: SRAM devices are disclosed that utilize write assist circuits to improve the logical transitions of bit lines. In one embodiment, an SRAM device includes a pair of complimentary bit lines traversing a memory cell array for writing data to memory cells. The bit lines have a first end and a second end. A pair of complimentary write drivers is proximate to the first end of the bit lines that writes to the bit lines. A write assist circuit is proximate to the second end of the bit lines that receives a pre-charge signal to assist the write drivers in transitioning the bit lines from a logical zero state to a logical one state. The write assist circuit also receives a boost signal to assist the write drivers in transitioning the bit lines from a logical one state to a logical zero state.

Abstract: Word line assist circuits are disclosed for high performance sub-micron SRAM designs. One embodiment is an SRAM device that includes a memory cell array and a pair of word lines that traverse the memory cell array for selecting memory cells. The SRAM device further includes a pair of word line drivers, each coupled to one of the word lines. The SRAM device further includes a word line assist circuit coupled to the pair of word lines that receives an enable signal. Responsive to receiving the enable signal, the word line assist circuit assists the first word line driver and the second word line driver in transitioning their respective word lines from a logic level zero to a logic level one in response to a voltage differential between the word lines.

Abstract: An array of memory cells on an integrated circuit device includes a plurality of memory cells arranged in at least one column. Each of the memory cells includes a plurality of transistors forming two complementary memory nodes. Each of the complementary memory nodes is connected to a respective pair of pull-up or pull-down transistors, which are connected in series and have a shared node between them. For a particular one of the memory cells, one of the shared nodes associated with one of the complementary memory nodes is directly connected to a corresponding respective shared node associated with a corresponding complementary memory node in a second one of the memory cells, and another of the shared nodes associated with another of the complementary memory nodes is directly connected to a corresponding shared node associated with a corresponding complementary memory node in a third one of the memory cells.

Abstract: Systems, methods, and devices for bearer independent protocol gateway performance optimization are described. In one aspect, a bearer independent protocol gateway is provided in the device which includes a traffic analyzer configured to detect when HTTP transaction(s) (request and corresponding responses) is/are completed and to switch to the next socket as soon as the transaction is completed, without necessarily waiting for the TCP socket to be closed. For example, when the gateway detects that the response is complete, it may push the current socket back into a socket queue and start serving the next socket.

Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.

Abstract: The present disclosure provides a prostacyclin coated implant to enhance fracture repair and bone formation comprising: an implant; and a prostacyclin coating comprising a prostacyclin compound disposed in a polymer coating the implant, wherein the prostacyclin coating releases the prostacyclin compound which enhances fracture repair and bone formation.

Abstract: A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test.

Abstract: Systems, methods, and devices relating to operating a power generation facility to contribute to the stability of the power transmission system. A controller operates on the power generation facility to modulate real power or reactive power or both in a decoupled manner to contribute to the stability of the power transmission system. Real power produced by the power generation facility can be increased or decreased between zero and the maximum real power available from the PV solar panels, as required by the power system. Reactive power from the power generation facility can be exchanged (injected or absorbed) and both increased or decreased as required by the power transmission system. For solar farms, the solar panels can be connected or disconnected, or operated at non-optimal power production to add or subtract real or reactive power to the power transmission system.

Abstract: The process of the present invention relates to a method for the synthesis of a 1,4-diphenylazetidinone of formula (VIII) by using novel oxime intermediates.

Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.