Patents by Inventor Rajiv N. Pathak

Rajiv N. Pathak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5631472
    Abstract: An in-situ method is disclosed for highly accurate lattice matching using reflection high energy electron diffraction dynamics. The method includes the steps of providing a substrate of a first semiconductor material and initiating growth of a second semiconductor material thereon. The oscillation amplitude of intensity I of waveform cycles is monitored using reflection high energy electron diffraction. A maximum intensity I.sup.+ and a minimum intensity I.sup.- is determined over a predetermined number of waveform cycles. The intensity drop .DELTA.I from initial reflectivity to minimum reflectivity of the waveform cycles is determined and normalized figure of merit FM is calculated for the predetermined number of waveform cycles using the relationship: ##EQU1## The fluxes of the second semiconductor material are then adjusted to maximize FM and optimize matching.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 20, 1997
    Assignee: Lucent Technologies Inc.
    Inventors: John E. Cunningham, Keith W. Goossen, Rajiv N. Pathak
  • Patent number: 5589404
    Abstract: A monolithically integrated, optoelectronic VLSI circuit is fabricated by growing optical devices on the compound semiconductor surface of a VLSI chip or wafer having pre-existing electronic devices formed thereon. In accordance with an illustrative embodiment of the present invention, a large array of surface normal optical modulating devices such as multiple quantum well modulators is grown on an impurity free surface of a VLSI chip having an array of FETs already provided thereon. The growth of such devices takes place at temperatures below 430.degree. C. on a compound semiconductor surface which has a highly ordered atomic structure. An optoelectronic switch constructed in this manner is capable of addressing electronic chips in systems handling 10,000 or more input/output optical beams.
    Type: Grant
    Filed: August 1, 1994
    Date of Patent: December 31, 1996
    Assignee: Lucent Technologies Inc.
    Inventors: John E. Cunningham, Keith W. Goossen, William Y. Jan, Rajiv N. Pathak, James A. Walker
  • Patent number: 5480813
    Abstract: An in-situ method is disclosed for highly accurate lattice matching using reflection high energy electron diffraction dynamics. The method includes the steps of providing a substrate of a first semiconductor material and initiating growth of a second semiconductor material thereon. The oscillation amplitude of intensity I of waveform cycles is monitored using reflection high energy electron diffraction. A maximum intensity I.sup.+ and a minimum intensity I.sup.- is determined over a predetermined number of waveform cycles. The intensity drop .DELTA.I from initial reflectivity to minimum reflectivity of the waveform cycles is determined and a normalized figure of merit FM is calculated for the predetermined number of waveform cycles using the relationship: ##EQU1## The fluxes of the second semiconductor material are then adjusted to maximize FM and optimize lattice matching.
    Type: Grant
    Filed: June 21, 1994
    Date of Patent: January 2, 1996
    Assignee: AT&T Corp.
    Inventors: John E. Cunningham, Keith W. Goossen, Rajiv N. Pathak