Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface having a first bi-directional channel and a second bi-directional channel. The interface operates in one of a first operational state and a second operational state, and performs an exemplary power-saving scheme if it is operating in the second operational state. The interface may detect a plurality of power states and initiate the power-saving scheme based on the detected power state. The plurality of power states may comprise a first power state (low current mode), a second power state (high current mode), and a third power state (mid-current mode).

Abstract: The subject technology receives, in a computing process, a user defined function, the user defined function including code related to at least one operation to be performed. The subject technology determines by a security manager whether performing the at least one operation is permitted, the security manager determines restrictions, based at least in part on a security policy. The subject technology performs the at least one operation. The subject technology sends a result of the at least one operation to the computing process, where sending the result of the at least one operation utilizes a data transport mechanism that supports a network transfer of columnar data.

Abstract: The subject technology receives, in a computing process, a user defined function, the user defined function including code related to at least one operation to be performed. The subject technology determines by a security manager whether performing the at least one operation is permitted, the security manager determines restrictions, based at least in part on a security policy. The subject technology performs the at least one operation. The subject technology sends a result of the at least one operation to the computing process, where sending the result of the at least one operation utilizes a data transport mechanism that supports a network transfer of columnar data.

Abstract: The subject technology receives, in a first computing process, a user defined function, the user defined function including code related to at least one operation to be performed. The subject technology sends a request based at least in part on the at least one operation to a second computing process to perform. The subject technology determines, by a security manager executing within the second computing process, whether performing the at least one operation is permitted, the security manager determines restrictions, based at least in part on a security policy, on operations executing within a sandbox environment provided by the second computing process. The subject technology performs, in the second computing process, the at least one operation, the security manager executing within the second computing process.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an output buffer. The output buffer is configured to perform in both a DP mode and an HDMI mode, as well as meet certain compliance conditions in an HDMI compliance testing mode. The output buffer includes a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode. The plurality of transistors and resistors are arranged to reduce leakage current during the HDMI compliance testing mode.

Abstract: The subject technology receives, in a first computing process, a user defined function, the user defined function including code related to at least one operation to be performed. The subject technology sends a request based on the at least one operation to a second computing process to perform, the second computing process being different than the first computing process and comprising a sandbox for executing the at least one operation. The subject technology receives, by the second computing process, the request. The subject technology determines, using at least a security policy, whether performing the at least one operation is permitted. The subject technology performs, in the second computing process, the least one operation. The subject technology sends, by the second computing process, a result of the at least one operation to the first computing process.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an auxiliary channel. The auxiliary channel may include a first PMOS transistor connected between two terminals of the auxiliary channel and a second PMOS transistor connected to one of the two terminals, via a resistor, at a first end and to a gate terminal of the first PMOS. The auxiliary channel may further include a support circuit connected to the gate terminals of both the first and second PMOS transistors.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.

Abstract: A probe card assembly includes a probe card, an interposer and a probe array. The probe array includes a plurality of closely spaced pins, each pin includes a post and a beam, and each beam has a first end attached to the top of a post and a second end for contacting an integrated circuit. A bead on the second end of the beam assures that the free end of the beam will contact an IC first. For contacts on a grid, the beams extend diagonally relative to the rows and columns of the grid, enabling the beams to be longer. For contacts in a row on centers closer than the pins, two rows of pins straddle the contacts and the beams extend toward the contacts from opposite sides of the contacts. The probe array can be formed on the high density side of the interposer.