Abstract: The present disclosure in some embodiments relates to a computer-based method for improving the pharmaceutical understanding of a user. The method includes receiving medication data from a source, wherein the medication data is related to a user's prescribed, dispensed, or claimed medicines; associating a unique ID for each user with the medication data for the user; providing a user interface, whereby the data for a user is accessible to the user only after the user has provided an authentication, wherein the medication data accessible to the user via the user interface comprises the one or more medications the user is taking.

Abstract: The present disclosure in some embodiments relates to a computer-based method for improving the pharmaceutical understanding of a user. The method includes receiving medication data from a source, wherein the medication data is related to a user's prescribed, dispensed, or claimed medicines; associating a unique ID for each user with the medication data for the user; providing a user interface, whereby the data for a user is accessible to the user only after the user has provided an authentication, wherein the medication data accessible to the user via the user interface comprises the one or more medications the user is taking.

Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate at which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.

Abstract: A method for constructing a Schottky diode in an integrated circuit on a semiconductor substrate (18) includes forming a mask layer (22) over a region (12) of the semiconductor substrate which the Schottky diode is to be formed. First portions of said mask layer (22) are removed to expose first regions (11) of said substrate (18). At least one semiconductor processing step is performed prior to the formation of the Schottky diode, which has processing temperature above about 450.degree. C. in said first regions (11) of said substrate (18), such as forming TiSi.sub.2 (33-35) in portions of an FET device in the integrated circuit. A second portion of said mask layer (22) is removed to expose a second region (12) of said semiconductor substrate (18) at which said Schottky diode is to be formed, and a region (48) is formed in said semiconductor substrate (18) comprising a metal and a material of said semiconductor substrate (18) in said second region (12), such as platinum silicide.

Abstract: A method for providing programmable devices in which an insulation layer, such as an oxide (20), TEOS, or the like, is formed during a BiCMOS integrated circuit fabrication process includes forming a first conductor fuse layer (22), for example of TiW or the like, on the insulation layer (20). The fuse layer (22) may then be patterned, and a second insulation layer (23) formed over it. Alternatively, the fuse layer (53) may be left unpatterned and one or more conductor layers (35,36) may be formed over the fuse layer (53). The conductor layer (35,36) is patterned, and the fuse layer (53) thereafter patterned using the conductor layer (35,36) as an etch mask. In either case, contact holes (26) are formed in the insulation layer (20) to regions (14,15) to which contact is desired under the insulation layer (20).

Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Abstract: A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter strucure (60). A collector region (90) and an extrinsic base region (100) are formed in the semicondcutor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: A process is disclosed with integrated steps for fabricating bipolar and CMOS transistors. Mask, patterning and implanting steps are highly integrated to reduce the fabrication complexity. The integrated steps include a split level polysilicon step wherein PMOS and NMOS gate conductors and a bipolar emitter structure is formed. The polysilicon is heavily doped which forms MOS transistor gate electrodes, and another high impurity concentration area which is later diffused into an underlying bipolar base region. Small area, high performance transistors can be fabricated with laterally extending contact strips. Alignment of electrode metallization patterns is thus less critical.

Abstract: An integrated circuit including a high value resistor (17d) is formed by using an amorphous silicon layer. The amorphous silicon layer may also be used to form the second plate (34) of a capacitor (17c) and a fuse (30). In the second embodiment of the invention, the amorphous silicon layer (92) is formed after the formation of the devices to avoid any additional high temperature cycles.

Abstract: Disclosed is a bipolar transistor and a method of fabrication thereof compatible with MOSFET devices. A transistor intrinsic base region (54) is formed in the face of a semiconductor well (22), and covered with a gate oxide (44). The gate oxide (44) is opened, and doped polysilicon is deposited thereover to form a polyemitter structure (68) in contact with the base region (54). Sidewall oxide (82, 84) is formed on the polyemitter structure (60). A collector region (90) and an extrinsic base region (100) are formed in the semiconductor well (22) and self aligned with respect to opposing side edges of the polyemitter sidewall oxide (82, 84).

Abstract: A process for making a metal fuse link in a MOS or CMOS process which includes depositing a refractory metal or metal alloy over an already deposited multi-level oxide and patterning the deposited metal or metal alloy so that it has a fusing segment between and integral with expanded segments such that the length and cross sectional area of the fusing segment is sufficiently small so that the fusing current therethrough is less than 20 milliamperes. The fuse and surrounding circuitry is covered with a passivation layer and contacts formed in the passivation layer to the expanded segments.

Abstract: An apparatus and method of photolithography with phase conjugate optics having a pump nonlinear medium for producing four way mixing of a beam of coherent electromagnetic radiation incident to said nonlinear medium with a spatically modulated representation of image thereon. The nonlinear medium producing by the phenomenon of four way mixing. A phase conjugated beam having a representation of the image spatically amplitude modulated thereon. The phase conjugated beam is directed toward a surface sensitive to electromagnetic radiation.

Abstract: A method for selectively heating an insulating layer on a semiconductor structure by a high energy transient radiation source to a temperature sufficient to cause reflow without any significant heating of the regions adjacent to or underlying the insulating layer. In one embodiment a laser tuned to the absorption wavelength of the insulating material is scanned over the surface of the semiconductor structure. In another embodiment an insulating layer and an underlying or adjacent semiconductor layer are concurrently heated by a laser tuned to an absorption wavelength common to both in order to maintain the integrity of the interface therebetween. In a further embodiment the depth of heating in an insulating layer is controlled by selecting an appropriate dwell time for a continuous wave laser and a pulse duration for a pulsed laser.

Abstract: In order to produce wafers suitable for fabrication of integrated circuits, an ingot of raw silicon must undergo a process which includes several steps. The ingot must be sawed into slices, the slices edge ground to remove roughness of the edges, lapped to remove as much saw damage as possible, stress relief etched to remove as small a damaged area as possible, then polished. Each of these steps requires removal of some of the material of the slice. The use of laser annealing reduces the amount of surface removed, as it repairs some surface damage, smoothes the surface, and when accomplished in a partial vacuum, improves the chemical composition of the material as related to electrical activity.