Patents by Inventor Rajiv Ranade
Rajiv Ranade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240107162Abstract: A method for image enhancement includes capturing multiple input images of a scene, including at least a first input image having a first field of view (FOV) captured with a first focal depth and a second input image having a second FOV captured with a second focal depth. The input images in the sequence are preprocessed so as to align the images. The aligned images are processed in a neural network, which generates an output image having an extended depth of field encompassing at least the first and second focal depths.Type: ApplicationFiled: July 6, 2023Publication date: March 28, 2024Inventors: Dan C. Lelescu, Rohit Rajiv Ranade, Noah Bedard, Brian McCall, Kathrin Berkner Cieslicki, Michael W. Tao, Robert K. Molholm, Toke Jansen, Vladimir Krneta
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Publication number: 20080032428Abstract: A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.Type: ApplicationFiled: October 15, 2007Publication date: February 7, 2008Inventors: Gary Behm, Teresita Magtoto, Rajiv Ranade
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Publication number: 20070056927Abstract: A process and system for anisoptropically dry etching through a doped silicon layer is described. The process chemistry comprises a nitrogen containing gas and a fluorocarbon gas. For example, the process chemistry comprises CF4, C4F8 and N2.Type: ApplicationFiled: September 14, 2005Publication date: March 15, 2007Inventors: Len Tsou, Rajiv Ranade, George Kaplita, Hongwen Yan, Rich Wise, Akiteru Ko
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Publication number: 20060255010Abstract: A method and system for controlling a dimension of an etched feature. The method includes: measuring a mask feature formed on a top surface of a layer on a substrate to obtain a mask feature dimension value; and calculating a mask trim plasma etch time based on the mask feature dimension value, a mask feature dimension target value, a total of selected radio frequency power-on times of a plasma etch tool since an event occurring to a chamber or chambers of a plasma etch tool for plasma etching the layer, and an etch bias target for a layer feature to be formed from the layer where the layer is not protected by the mask feature during a plasma etch of the layer.Type: ApplicationFiled: May 10, 2005Publication date: November 16, 2006Applicant: International Business Machines CorporationInventors: Gary Behm, Teresita Magtoto, Rajiv Ranade
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Publication number: 20050260859Abstract: A method is provided for patterning a semiconductor region, which can be heavily doped. A patterned mask is provided above the semiconductor region. A portion of the semiconductor region exposed by the patterned mask is etched in an environment including a polymerizing fluorocarbon, e.g., a chlorine-free fluorocarbon having a high ratio of carbon to fluorine atoms, and at least one non-polymerizing substance selected from the group consisting of non-polymerizing fluorocarbons, e.g. those having a low ratio of carbon to fluorine atoms, and hydrogenated fluorocarbons. The method preferably passivates the sidewalls of the patterned semiconductor region, such that a lower region of semiconductor material below the patterned region can be directionally etched without eroding the thus passivated patterned region.Type: ApplicationFiled: May 21, 2004Publication date: November 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Sadanand Deshpande, Rajiv Ranade, George Worth
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Publication number: 20050051820Abstract: A method of fabricating a magnetic tunnel junction (MTJ) device is provided. A patterned hard mask is oxidized to form a surface oxide thereon. An MTJ stack is etched in alignment with the patterned hard mask after the oxidizing of the patterned hard mask. Preferably, the MTJ stack etch recipe includes chlorine and oxygen. Etch selectivity between the hard mask and the MTJ stack is improved.Type: ApplicationFiled: September 10, 2003Publication date: March 10, 2005Inventors: George Stojakovic, Rajiv Ranade, Ihar Kasko, Joachim Nuetzel, Keith Milkove, Russell Allen, Young Lee, Kim Lee
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Publication number: 20050009295Abstract: A method of forming at least one deep trench structure having an increased trench depth is provided. The method includes providing at least one deep trench having sidewalls that extend to a common bottom wall in a surface of a substrate. Each deep trench has initial dimensions that are wider than targeted dimensions for the deep trenches. To reduce the initial dimensions to that of the targeted dimensions, an epitaxial silicon film is formed selectively or non-selectively on at least some portions of the sidewalls using a low-temperature ultra-high vacuum epitaxial silicon growth tehnique.Type: ApplicationFiled: July 27, 2004Publication date: January 13, 2005Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, INFINEON TECHNOLOGIES NORTH AMERICA CORPORATIONInventors: Kevin Chan, Subhash Kulkarni, Gangadhara Mathad, Rajiv Ranade
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Patent number: 6821900Abstract: A method for etching trenches in a substrate secures a wafer to an electrode in a plasma chamber and heats the wafer to a temperature of greater than 200 degrees Celsius. The wafer is exposed to a reactive plasma to etch trenches into the substrate of the wafer with minimal redeposition of etch by-products to avoid pinching off the trench and to promote further etching.Type: GrantFiled: January 9, 2001Date of Patent: November 23, 2004Assignees: Infineon Technologies AG, International Business MachinesInventors: Satish Athavale, Rajiv Ranade, Munir Naeem, Gangadhara Swami Mathad
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Patent number: 6809005Abstract: The present invention provides methods of producing trench structures having substantially void-free filler material therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: GrantFiled: March 12, 2003Date of Patent: October 26, 2004Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Publication number: 20040180510Abstract: The present invention provides methods of producing trench structures having substantially void-free filler materials therein. The fillers may be grown from a liner material such as polysilicon formed along the sidewalls of the trench. Previously formed voids may be healed by exposing the voids and growing epitaxial silicon.Type: ApplicationFiled: March 12, 2003Publication date: September 16, 2004Applicants: Infineon Technologies North America Corp., International Business Machines CorporationInventors: Rajiv Ranade, Gangadhara S. Mathad, Kevin K. Chan, Subhash B. Kulkarni
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Patent number: 6768155Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.Type: GrantFiled: May 14, 2003Date of Patent: July 27, 2004Assignee: Infineon Technologies AGInventors: Venkatachalam C. JaiPrakash, Rajiv Ranade
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Publication number: 20040000683Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.Type: ApplicationFiled: May 14, 2003Publication date: January 1, 2004Applicant: Infineon Technologies North America Corp.Inventors: Venkatachalam C. JaiPrakash, Rajiv Ranade
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Patent number: 6605504Abstract: Semiconductor devices having trenches with buried straps therein preventing lateral out-diffusion of dopant are provided along with methods of fabricating such semiconductor devices.Type: GrantFiled: June 28, 2002Date of Patent: August 12, 2003Assignee: Infineon Technologies AGInventors: Venkatachalam C. JaiPrakash, Rajiv Ranade
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Patent number: 6544838Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.Type: GrantFiled: March 13, 2001Date of Patent: April 8, 2003Assignees: Infineon Technologies AG, International Business Machines CorporationInventors: Rajiv Ranade, Munir D. Naeem, Gangadhara S. Mathad
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Patent number: 6489249Abstract: In a method of etching a wafer in a plasma etch reactor, the improvement of conducting etching to reduce or eliminate “black silicon” comprising: a) providing a plasma etch reactor comprising walls defining an etch chamber; b) providing a plasma source chamber remote from and in communication with the etch chamber to provide a plasma to the etch chamber, and a wafer chuck or pedestal disposed in the etch chamber to seat a wafer; c) providing a dielectric wall in proximity to and around a periphery of the wafer; d) providing a modification to a lower Rf electrode by interposing conductor means into an extension of Vdc flat sheath boundary relationship to the dielectric wall means and the wafer or in substitution for the dielectric wall; e) forming a plasma within the plasma source chamber and providing the plasma to the etch chamber; and f) supplying Rf energy to the wafer chuck to assist etching of the wafer by forming electric fields between the upper surface of the wafer and the walls of tType: GrantFiled: June 20, 2000Date of Patent: December 3, 2002Assignee: Infineon Technologies AGInventors: Gangadhara S. Mathad, Rajiv Ranade
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Publication number: 20020132422Abstract: A method for etching trenches includes providing a patterned mask stack on a substrate. A trench is etched in the substrate by forming a tapered-shaped trench portion of the trench, which narrows with depth in the substrate by employing a first plasma chemistry mixture including O2, HBr and NF3. An extended portion of the trench is formed by etching a second profile deeper and wider than the tapered-shaped trench portion in the substrate by employing a second plasma chemistry mixture including O2, HBr and SF6 or F2.Type: ApplicationFiled: March 13, 2001Publication date: September 19, 2002Applicant: Infineon Technologies North America Corp.Inventors: Rajiv Ranade, Munir D. Naeem, Gangadhara S. Mathad
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Patent number: 6103585Abstract: A vertical trench in a silicon wafer for use in forming the storage capacitor of a DRAM is etched by reactive ion etching in a manner to have a profile that has multiple waists. This profile is obtained by varying the rate of flow of coolant in the base member on which the silicon wafer is supported during the reactive ion etching to vary the temperature of the silicon wafer during the etching. Alternatively, the multiple waists are achieved by either by varying the ratio of the different gases in the etching chamber or the total gas pressure in the chamber.Type: GrantFiled: June 9, 1998Date of Patent: August 15, 2000Assignee: Siemens AktiengesellschaftInventors: Alexander Michaelis, Rajiv Ranade, Bertrand Flietner