Abstract: A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage.

Abstract: A copper electroplating bath composition and a method of copper electroplating to improve gapfill are provided. The method of electroplating includes providing an aqueous electroplating composition, comprising copper, at least one acid, at least one halogen ion, an additive including an accelerating agent, a suppressing agent, and a suppressing-accelerating agent, and the solution and mixture products thereof; contacting a substrate with the plating composition; and impressing a multi-step waveform potential upon the substrate, wherein the multi-step waveform potential includes an entry step, wherein the entry step includes a first sub-step applying a first current and a second sub-step applying second current, the second current being greater than the first current. The accelerating agent is provided in concentration of greater than 1.

Abstract: A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage.

Abstract: A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage. In one embodiment, the voltage of a plating cell including a reference wafer which has substantially complete Cu seed coverage is measured. A reference resistance of the plating cell with the reference wafer is determined. The voltage of the plating cell including a calibration wafer which has no or insufficient seed coverage at its edge is measured. A calibration resistance of the plating cell with the calibration wafer is determined. An error trigger based on a comparison of the reference resistance with the calibration resistance is selected.

Abstract: Embodiments of the invention provide methods for electroplating a substrate that substantially reduce or eliminate protrusions and decrease WID thickness variations. The number of protrusions formed on the plating surface is highly dependent upon the electroplating current density. Embodiments of the invention vary the electroplating current waveform by implementing an initial current step sufficient to fill substrate features and a terminal current step sufficient to achieve the specified plating thickness while suppressing protrusions and within die thickness variations.

Abstract: A copper electroplating bath composition and a method of copper electroplating to improve gapfill are provided. The method of electroplating includes providing an aqueous electroplating composition, comprising copper, at least one acid, at least one halogen ion, an additive including an accelerating agent, a suppressing agent, and a suppressing-accelerating agent, and the solution and mixture products thereof; contacting a substrate with the plating composition; and impressing a multi-step waveform potential upon the substrate, wherein the multi-step waveform potential includes an entry step, wherein the entry step includes a first sub-step applying a first current and a second sub-step applying second current, the second current being greater than the first current. The accelerating agent is provided in concentration of greater than 1.

Abstract: A die is provided with an insulation layer and an interconnect. The interconnect has been recrystallized to reduce void content.

Abstract: A method and apparatus are described that use cell voltage and/or current as monitor to prevent electrochemical deposition (e.g., electroplating) tools from deplating wafers with no or poor metal (e.g., Cu) seed coverage.

Abstract: An electroplating system is provided with a rotatable head assembly including a substrate holder to secure a substrate for entry into a bath of electrolyte; and a head tilt mechanism including a stepper motor connected to the rotatable head assembly and configured to control bath entry parameters for optimal surface wetting of the substrate, upon bath entry for electroplating the substrate free of electroplating defects, including, but not limited to, swirl defects.

Abstract: Embodiments of the invention provide methods for electroplating a substrate that substantially reduce or eliminate protrusions and decrease WID thickness variations. The number of protrusions formed on the plating surface is highly dependent upon the electroplating current density. Embodiments of the invention vary the electroplating current waveform by implementing an initial current step sufficient to fill substrate features and a terminal current step sufficient to achieve the specified plating thickness while suppressing protrusions and within die thickness variations.

Abstract: A wafer is prepared for electroplating via a spin, rinse and dry process performed on the wafer prior to electroplating. The process may be performed in a standalone tool or may be performed in a preclean module integrated into an electroplating tool.

Abstract: An improvement in a metal stack used for interconnecting structures in an integrated circuit. The improvement comprises the entrapping in a titanium layer of nitrogen at the interface where the titanium layer contacts a bulk conductor layer such as an aluminum-copper alloy layer. The entrapped nitrogen prevents the formation of any substantial amount of titanium aluminide thereby reducing current densities and also improving the electromigration properties of the stack. As currently preferred, the nitrogen is entrapped in approximately the first 30.ANG. of the titanium layer.

Abstract: The present invention generally involves the fabrication of semiconductor devices so as to reduce the active region to interconnect interface resistivity. Fabrication begins by forming active regions on a semiconductor device. Next, a titanium metal of approximately 900 .ANG. thickness is deposited on the semiconductor device. The semiconductor device is then annealed in a single step to form the interconnects.