Patents by Inventor Rajive Dhar

Rajive Dhar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060193267
    Abstract: An input detector detects the bit rate and signal type of multiple signals at corresponding multiple interface ports. A master controller coupled to the detector sends control signals to different types of framers such that signals received at one of the multiple interface ports is operated on by a framer corresponding to the signals format type. In addition, an Ethernet aggregator may combine multiple Ethernet frames of different sizes into a single frame so when it is mapped into a SONET frame, essentially all of the SONET frame is used. A SONET mapper generates and inserts information into a frame that identifies the contents of the information contained therein. At a receiving end, the mapper can determine from this information the contents, and can instruct a controller which framer/unframer to send the frame information to.
    Type: Application
    Filed: February 21, 2006
    Publication date: August 31, 2006
    Inventors: Rajive Dhar, Anita Chowdhry, Rajesh Subramaniam
  • Patent number: 5943591
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: August 24, 1999
    Assignee: VLSI Technology
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5885856
    Abstract: A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).
    Type: Grant
    Filed: August 21, 1996
    Date of Patent: March 23, 1999
    Assignee: Motorola, Inc.
    Inventors: Percy V. Gilbert, Subramoney Iyer, Bradley P. Smith, Matthew A. Thompson, Kevin Kemp, Rajive Dhar
  • Patent number: 5795815
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: August 19, 1996
    Date of Patent: August 18, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers
  • Patent number: 5686171
    Abstract: A method for forming a scribe line on a semiconductor wafer including the steps of: (a) providing a semiconductor substrate; and (b) sequentially providing a plurality of layers over the semiconductor substrate of alternating conductive and insulating types, where each of the layers is provided with an elongated opening is formed relative to a desired scribe line position, and where the openings of at least some of the plurality of layers are wider than openings of preceding layers such that at least one sidewall of a completed scribe line has a pronounced slope extending outwardly from its base. The structure of the present invention is, therefore, a scribe line having sloped sidewalls that greatly reduces scribe line contamination problems and enhances planarization during subsequent spin-on-material processes. The scribe lines can either be elongated openings in the layers, or an elongated mesa formed in the layers.
    Type: Grant
    Filed: December 30, 1993
    Date of Patent: November 11, 1997
    Assignee: VLSI Technology, Inc.
    Inventors: Edward R. Vokoun, Miguel A. Delgado, Gregory N. Carter, Brian D. Richardson, Rajive Dhar, Elizabeth A. Chambers