Patents by Inventor Rajive Kumar

Rajive Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150162750
    Abstract: Systems, methods, and devices relating to operating a power generation facility to contribute to the stability of the power transmission system. A controller operates on the power generation facility to modulate real power or reactive power or both in a decoupled manner to contribute to the stability of the power transmission system. Real power produced by the power generation facility can be increased or decreased between zero and the maximum real power available from the PV solar panels, as required by the power system. Reactive power from the power generation facility can be exchanged (injected or absorbed) and both increased or decreased as required by the power transmission system. For solar farms, the solar panels can be connected or disconnected, or operated at non-optimal power production to add or subtract real or reactive power to the power transmission system.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 11, 2015
    Inventor: Rajiv Kumar VARMA
  • Publication number: 20150162932
    Abstract: A method for compensating for panel capacitance the associated current is proposed, wherein the mutual capacitances of a capacitance sensing array are selectively coupled to drive voltages and to a self capacitance under test.
    Type: Application
    Filed: June 27, 2014
    Publication date: June 11, 2015
    Inventors: Andrew Page, Timothy Williams, Rajiv Kumar Singh, Kaveh Hosseini, Jonathan Peterson, Andriy Maharyta
  • Patent number: 9040688
    Abstract: The process of the present invention relates to a method for the synthesis of a 1,4-diphenylazetidinone of formula (VIII) by using novel oxime intermediates.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: May 26, 2015
    Assignee: LUPIN LIMITED
    Inventors: Dhananjai Srivastava, Rajiv Kumar Shakya, Namrata Anil Chaudhari, Inamus Saqlain Ansari, Girij Pal Singh
  • Publication number: 20150138863
    Abstract: An SRAM device includes a plurality of memory cells and a first metallization layer comprising a first pair of bitlines operable to couple to a first segment of the memory cells. The device also includes a second metallization layer comprising a second pair of bitlines operable to couple to a second segment of the memory cells and a write assist line interleaved with the first and second metallization layers to provide a substantially constant coupling capacitance with each of the first and second pairs of bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Rajiv Kumar Roy, Donald Albert Evans, Rasoju Veerabadra Chary, Rahul Sahu
  • Publication number: 20150138876
    Abstract: An SRAM device includes a segmented memory cell array with a plurality of memory cells. Each segment of memory cells includes a bitline coupled to the memory cells in the segment. The SRAM device further includes a global bitline traversing the segmented memory cell array and communicatively coupled to the memory cell segments via the local bitlines for writing to the memory cells. The SRAM device further includes a global input/output module operable to hold the global bitline at logical zero, to toggle the global bitline to logical one when data is to be written, to select one of the segments of memory cells for writing after the global bitline has been toggled, and to toggle the global bitline to logical zero when data is written to the selected memory cell segment to provide a negative boost voltage to the local bitline of the selected memory cell segment.
    Type: Application
    Filed: January 13, 2014
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Rajiv Kumar Roy, Rasoju Veerabadra Chary
  • Publication number: 20150138864
    Abstract: Systems and methods presented herein provide a memory system which includes a memory cell array. The memory cell array includes first and second segments with corresponding local bitlines connected to one or more memory cells. The memory cell array also includes first and a second metallization layers. The second metallization layer includes first and second global bitlines. The first metallization layer includes local bitlines. In each of the first segments, local bitlines are connected to one of the first global bitlines. In each of the second segments, local bitlines are connected to one of the second global bitlines.
    Type: Application
    Filed: November 21, 2013
    Publication date: May 21, 2015
    Applicant: LSI CORPORATION
    Inventors: Donald Albert Evans, Rasoju Veerabadra Chary, Rajiv Kumar Roy, Rahul Sahu
  • Patent number: 9019673
    Abstract: Systems, methods, and devices relating to fault detection and short circuit current management support in power transmission and distribution networks using multiple inverter based power generation facilities. A fault detection process uses the waveshape (or the rate of change of the current) of the distributed generator output short circuit current to determine if a trip signal is required to disconnect the inverter based power generation facility from the transmission and distribution network. The process operates on DGs such as photovoltaic (PV) based solar farm. The present invention applies to the entire 24-hour period operation of inverter based DGs (e.g., solar farms, wind farms, fuel cell based DGs, etc.).
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 28, 2015
    Inventors: Rajiv Kumar Varma, Shah Arifur Rahman
  • Patent number: 8892683
    Abstract: A mobile computing device comprising a wireless transmitter/receiver, processing components, memory components, and a web browser. The web browser is adapted to, initiate a first request to view a website comprising a plurality of objects, and, receive the plurality of objects in a first order. The web browser is further adapted to, determine a new order for requesting the plurality of objects, and, initiate a request to view the website comprising the plurality of objects in the new order. The web browser is also adapted to receive the plurality of objects in the new order.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Bojin Liu, Lorenzo Vicisano, Rajiv Kumar Vijayakumar, Saumitra M. Das, Behrooz Khorashadi
  • Patent number: 8850307
    Abstract: One embodiment comprises a non-transitory, tangible computer readable storage medium, encoded with processor readable instructions to perform a method of displaying content in a web page. One method optimizes the order of HTTP requests made during the downloading of a web page or web application comprising a plurality of objects, and receiving a first portion of the plurality of objects in a first order. Additionally, (i) a viewable section of the web page, (ii) centers of the viewable section of the web page and each of the plurality of objects, and (iii) a distance from the center of the viewable section of the web page to the center of each of the plurality of objects may be determined. Furthermore, the objects may then be prioritized based on their distance from the center of the viewable section. A request to receive at least one additional portion of the objects in a second order based on the prioritization of the objects may then be sent.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: September 30, 2014
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Jan E. Hanssen, Rajiv Kumar Vijayakumar, Mark Bapst
  • Publication number: 20140241061
    Abstract: A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: LSI Corporation
    Inventors: Rajiv Kumar Roy, Disha Singh, Sahilpreet Singh
  • Publication number: 20140241028
    Abstract: A read-only memory (ROM) cell has first and second transistors connected in series between a true bit line and a voltage reference (e.g., ground), and third and fourth transistors connected in series between a complement bit line and the voltage reference. The gates of the first and third transistors are connected to a first word line, and the gates of the second and fourth transistors are connected to a second word line. The ROM cell is programmed to store any possible combination of two bits of information by appropriately (i) connecting the node between the first and second transistors to either the true bit line, the complement bit line, or the voltage reference and (ii) connecting the node between the third and fourth transistors to either the true bit line, the complement bit line, or the voltage reference.
    Type: Application
    Filed: February 27, 2013
    Publication date: August 28, 2014
    Applicant: LSI Corporation
    Inventors: Rajiv Kumar Roy, Vikash
  • Patent number: 8780615
    Abstract: In a memory device, a bitline write voltage is applied to a first bitline. A wordline voltage is applied to a first wordline for writing data to a first memory cell connected to the first wordline and the first bitline. The first bitline and the second bitline are electrically connected for charge sharing between the first bitline and the second bitline. A predetermined time after electrically connecting the first bitline and the second bitline, the first and the second bitline are electrically disconnected and the bitline write voltage is applied to the second bitline. The wordline voltage is applied to a second wordline for writing data to a second memory cell connected to the second wordline and the second bitline.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics International N.V.
    Inventors: Naveen Batra, Rajiv Kumar, Saurabh Agrawal
  • Publication number: 20140101027
    Abstract: Pools of money or loanable funds are created. The pool is assigned certain attributes. People, companies or entities are allowed to apply to the pools of loanable funds as loan applicants. The loan applications are aggregated and forwarded to a lender or creditor or on behalf of the creator of a pool to a lender. The creator can be a lending entity, a company or a person. The pools can be given a combination of characteristics that are considered the current and normal method of expressing loans and credit applications to the public as well as lenders and creditors.
    Type: Application
    Filed: October 4, 2013
    Publication date: April 10, 2014
    Inventors: Rajive Kumar JAIN, Ketan BHALLA
  • Patent number: 8691915
    Abstract: This disclosure relates generally to methods for the manufacture of transparent polymer compositions exhibiting refractive indices similar or even identical to the refractive index of polycarbonate. Also disclosed are polymer blends comprising the disclosed polymer compositions blended with one or more convention polycarbonate.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: April 8, 2014
    Assignee: SABIC Innovative Plastics IP B.V.
    Inventors: Rajiv Kumar Srivastava, James Louis DeRudder, Rajashakhar Totad, Robert Walter Venderbosch, Raja Krishnamurthy
  • Publication number: 20140085763
    Abstract: Systems, methods, and devices relating to fault detection and short circuit current management support in power transmission and distribution networks using multiple inverter based power generation facilities. A fault detection process uses the waveshape (or the rate of change of the current) of the distributed generator output short circuit current to determine if a trip signal is required to disconnect the inverter based power generation facility from the transmission and distribution network. The process operates on DGs such as photovoltaic (PV) based solar farm. The present invention applies to the entire 24-hour period operation of inverter based DGs (e.g., solar farms, wind farms, fuel cell based DGs, etc.).
    Type: Application
    Filed: March 14, 2013
    Publication date: March 27, 2014
    Inventors: Rajiv Kumar VARMA, Shah Arifur Rahman
  • Publication number: 20140059422
    Abstract: Systems and methods are herein disclosed for reducing power consumption, processor activity, network activity, and for improving a user experience during web browsing. More particularly, an ordering of IFrames, or other self-contained component within the mainframe, is modified in terms of network resources, memory resources, and processor resources in order to conserve user device resources. For instance, aspects of multicore processors and multichannel network connections are utilized to perform parallel operations on mainframe data packets and IFrame data packets when a webpage is downloaded. Since mainframes and IFrames are sourced from different URLs they can be received on separate communication channels and can be processed on different cores. Prioritization in memory storage between the two can also be used to enhance the speed with which the mainframe is loaded.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Applicant: QUALCOMM INNOVATION CENTER, INC.
    Inventors: Kavitha Vallari Devara, Bojin Liu, Rajiv Kumar Vijayakumar
  • Publication number: 20140046500
    Abstract: The invention provides systems, methods, and devices relating to the provision of system-wide coordinated control voltage regulation support in power transmission and distribution networks using multiple inverter based power generation facilities, which are coupled to the power transmission and distribution networks for minimizing transmission and distribution line losses. The invention uses a novel control method of inverter based Distributed Generators as Static Synchronous Compensator (STATCOM) in a way that provides a dynamic voltage regulation/control with the inverter capacity remaining after real power generation, thereby decreasing system line losses.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 13, 2014
    Inventor: Rajiv Kumar VARMA
  • Publication number: 20140003248
    Abstract: Systems, methods, and devices for bearer independent protocol gateway performance optimization are described. In one aspect, a bearer independent protocol gateway is provided in the device which includes a traffic analyzer configured to detect when HTTP transaction(s) (request and corresponding responses) is/are completed and to switch to the next socket as soon as the transaction is completed, without necessarily waiting for the TCP socket to be closed. For example, when the gateway detects that the response is complete, it may push the current socket back into a socket queue and start serving the next socket.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 2, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Michele Berionne, Rajiv Kumar Vijayakumar, Anil Kumar Taleppady, Damir Didjusto, Xiaomin Zhu, Jose Alfredo Ruvalcaba
  • Publication number: 20130327361
    Abstract: The present invention is in the field of laundry processes and devices. In particular the invention relates to the saving of water. It is an object of the present invention to reduce the water consumption in conventional washing methods, especially machine washing methods. It is found that the continuous pH controlled sequential dosing of an electrolyte, followed by dosing of a polymer and a solid liquid separation step during a full wash cycle of a washing machine, provides continuous clarification of the wash liquor and enables the continuous reuse of the water during said wash cycle.
    Type: Application
    Filed: December 14, 2011
    Publication date: December 12, 2013
    Inventors: Sarmistha Biswas, Debosree Chatterjee, Rajiv Kumar Garg, Rudra Saurabh Shresth, Dhanalakshmi Thirumeni
  • Publication number: 20130325553
    Abstract: Aspects of the present disclosure involve apparatus, systems and methods for generating and converting sales opportunities. The apparatus and system may involves an applicatoin and various possible graphical user interfaces (GUI's) running on some form of smart tablet type computing device that accesses geographical information, customer analytic information, and telecommunication infrastructure (or other technical infrastructure) and allows a user to define an optimal travel route between various possible customer based on geographic, customer and infrastructure criteria.
    Type: Application
    Filed: May 31, 2013
    Publication date: December 5, 2013
    Inventors: Yunas Nadiadi, Rajiv Kumar Singh, Luke Patrick Phillips, Jeffrey Kendall Storey, Paul Farnsworth, Mark William Martinet