Abstract: A novel automatic standardization and verification process for system design requirements in a product development project is disclosed. In one embodiment, a method for automatic standardization and verification of system design requirements in a product development project using a standardization and verification tool embedded in a computer aided design (CAD) application includes obtaining a desired standardized requirement from a requirements database, retrieving compliance criteria from the standardized requirement, obtaining one or more components associated with the standardized requirement from one or more data sources, and obtaining relevant extracted and derived attributes from the one or more components, associated with the standardized requirement.

Abstract: A novel automatic standardization and verification process for system design requirements in a product development project is disclosed. In one embodiment, a method for automatic standardization and verification of system design requirements in a product development project using a standardization and verification tool embedded in a computer aided design (CAD) application includes obtaining a desired standardized requirement from a requirements database, retrieving compliance criteria from the standardized requirement, obtaining one or more components associated with the standardized requirement from one or more data sources, and obtaining relevant extracted and derived attributes from the one or more components, associated with the standardized requirement.

Abstract: A method and system for providing simulation of an integrated circuit during development of the integrated circuit is disclosed. The integrated circuit has an island that includes an interface. The method and system include a snooper, a checker and a generator. The snooper is coupled with an interface and is for obtaining an output provided by the island during simulation. The checker is coupled with an interface and is for checking the output to determine whether the output is a desired output. The generator is coupled with an interface and is for providing an input to the interface during simulation. The generator is coupled with a test case that directs the generator.

Abstract: This system represents a customizable simulation model of an ATM/SONET Framer for System Level Verification and Performance-Characterization. An Asynchronous Transfer Mode (ATM) data processing ASIC interfaces with a Media Access Control (MAC) device that presents an electrical data path interface, called Universal Test & Operations PHY Interface for ATM (UTOPIA), using ATM protocol on the ASIC side and simplex optical interfaces using Synchronous Optical Network (SONET) protocol on the network side. Such a MAC device, commonly referred to as ATM/SONET Framer, provides one Receive and one Transmit interface to the network at various SONET line rates such as 155.52 Mbps (OC-3), 622.08 Mbps (OC-12), 2488.32 Mbps (OC-48), etc. The ATM and the SONET interfaces operate on different clock frequencies and thus represent two distinct clocking domains. The data interchange between the two clocking domains is achieved via FIFO buffer elements and associated control and status signals.

Abstract: A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.