Patents by Inventor Rajneesh Jaiswal
Rajneesh Jaiswal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7964517Abstract: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.Type: GrantFiled: January 29, 2009Date of Patent: June 21, 2011Assignee: Texas Instruments IncorporatedInventor: Rajneesh Jaiswal
-
Publication number: 20100190352Abstract: According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.Type: ApplicationFiled: January 29, 2009Publication date: July 29, 2010Inventor: Rajneesh JAISWAL
-
Publication number: 20100167552Abstract: A method of manufacturing an IC device includes providing a workpiece having least one dielectric layer disposed on a surface of the workpiece. The method also includes processing the dielectric layer to form a plurality of apertures in the dielectric layer, where the processing includes at least one micromask-prone process. The method further includes subsequent to the processing step, cryogenically treating the workpiece. In the method, the treating step removes particles deposited on or in the plurality of apertures during the processing step and maintains the plurality of apertures, where the particles are generated from micromask features resulting from the micromask-prone process.Type: ApplicationFiled: December 30, 2008Publication date: July 1, 2010Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Murlidhar Bashyam, Rajneesh Jaiswal, Jason R. Heine
-
Patent number: 7455448Abstract: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change ?Rs=Rsi?Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating ?Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of ?Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error.Type: GrantFiled: July 26, 2004Date of Patent: November 25, 2008Assignee: Texas Instruments IncorporatedInventors: Rajneesh Jaiswal, Eric W. Beach, Barbara M. Barnes
-
Publication number: 20080248599Abstract: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change Rs=Rsi?Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error.Type: ApplicationFiled: June 19, 2008Publication date: October 9, 2008Inventors: Rajneesh Jaiswal, Eric W. Beach, Barbara M. Barnes
-
Patent number: 7384855Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.Type: GrantFiled: October 26, 2006Date of Patent: June 10, 2008Assignee: Texas Instruments IncorporatedInventors: Rajneesh Jaiswal, H. Jerome Barber, Thomas E. Kuehl
-
Patent number: 7354854Abstract: Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap layer on the nickel layer. Nickel silicide bridging between the gate and source and/or drain is avoided or eliminated by using a chrome etching process to remove un-reacted nickel and nickel remnants from exposed surfaces of dielectric spacers (6A,B) located between the gate and source and between the gate and drain. The chrome etching process includes use of a solution including cerric ammonium nitrate, nitric acid, and acetic acid.Type: GrantFiled: May 24, 2005Date of Patent: April 8, 2008Assignee: Texas Instruments IncorporatedInventor: Rajneesh Jaiswal
-
Patent number: 7323751Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.Type: GrantFiled: June 3, 2003Date of Patent: January 29, 2008Assignee: Texas Instruments IncorporatedInventors: Eric Williams Beach, Rajneesh Jaiswal
-
Patent number: 7196398Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.Type: GrantFiled: March 4, 2005Date of Patent: March 27, 2007Assignee: Texas Instruments IncorporatedInventors: Rajneesh Jaiswal, H. Jerome Barber, Thomas E. Kuehl
-
Publication number: 20070048960Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.Type: ApplicationFiled: October 26, 2006Publication date: March 1, 2007Inventors: Rajneesh Jaiswal, H. Barber, Thomas Kuehl
-
Publication number: 20060267117Abstract: Nickel silicide contact regions are formed on a source (2), drain (3) and polycrystalline silicon gate (5) of an integrated circuit transistor by annealing it after a nickel layer has been deposited on the source, drain, and gate, with no cap layer on the nickel layer. Nickel silicide bridging between the gate and source and/or drain is avoided or eliminated by using a chrome etching process to remove un-reacted nickel and nickel remnants from exposed surfaces of dielectric spacers (6A,B) located between the gate and source and between the gate and drain. The chrome etching process includes use of a solution including cerric ammonium nitrate, nitric acid, and acetic acid.Type: ApplicationFiled: May 24, 2005Publication date: November 30, 2006Inventor: Rajneesh Jaiswal
-
Publication number: 20060199315Abstract: A method of preventing contact noise in a SiCr thin film resistor includes performing in situ depositions of a SiCr layer and then a TiW layer on a substrate without breaking a vacuum between the depositions, to prevent formation of any discontinuous oxide between the SiCr layer and the TiW layer. The SiCr and TiW layers are patterned to form a predetermined SiCr thin film resistor pattern and a TiW resistor contact pattern on the SiCr thin film resistor, and a metallization layer is provided to contact the TiW forming the resistor contact pattern.Type: ApplicationFiled: March 4, 2005Publication date: September 7, 2006Inventors: Rajneesh Jaiswal, H. Barber, Thomas Kuehl
-
Publication number: 20060019415Abstract: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change ?Rs=Rsi?Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating ?Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of ?Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error.Type: ApplicationFiled: July 26, 2004Publication date: January 26, 2006Inventors: Rajneesh Jaiswal, Eric Beach, Barbara Barnes
-
Publication number: 20040245575Abstract: A thin film resistor and at least one metal interconnect are formed in an integrated circuit. A first dielectric layer is formed over a metal interconnect layer. A thin film resistor is formed on the first dielectric layer and a second dielectric layer formed over the thin film resistor. Thin film resistor vias and the at least one trench are formed concurrently in the second dielectric layer. A trench via is then formed in the at least one trench. The trench via, the at least one trench and the thin film resistor vias are filled with a contact material layer to form thin film resistor contacts and at least one conductive line coupled to the metal interconnect layer.Type: ApplicationFiled: June 3, 2003Publication date: December 9, 2004Inventors: Eric Williams Beach, Rajneesh Jaiswal
-
Patent number: 6734076Abstract: A thin film resistor (55) is formed over an etch stop layer 40. Contact pads (65) are formed n the thin film resistor (55) and a dielectric layer (80) is formed over the thin film resistor (55). Metal structures (120 are formed above the thin film resistor (55) and metal (110) is used to fill a trench and via formed in the dielectric layer (80).Type: GrantFiled: March 17, 2003Date of Patent: May 11, 2004Assignee: Texas Instruments IncorporatedInventors: Rajneesh Jaiswal, Eric W. Beach
-
Publication number: 20040087047Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.Type: ApplicationFiled: October 6, 2003Publication date: May 6, 2004Inventors: Rajneesh Jaiswal, Chandrakant Patadia
-
Patent number: 6664166Abstract: A method for processing a partially fabricated semiconductor wafer having a layer of nichrome resistor material patterned to form a plurality of nichrome resistors on a surface of the wafer includes performing a wet pre-metallization cleaning step on the wafer surface, performing an RF argon plasma sputter etching process on the wafer surface, advancing the wafer into a second reactor without breaking a vacuum in either reactor, depositing a layer of metal on the surface, patterning the metal to form a predetermined metal interconnection pattern thereof, performing a stabilization bake cycles on the wafer, measuring the TCR of the nichrome resistor material, and rejecting the wafer if the measured TCR is greater than a predetermined value.Type: GrantFiled: September 13, 2002Date of Patent: December 16, 2003Assignee: Texas Instruments IncorporatedInventors: Rajneesh Jaiswal, Chandrakant Patadia
-
Patent number: 6517235Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems.Type: GrantFiled: May 31, 2001Date of Patent: February 11, 2003Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Zhong Yun Zhu, Rajneesh Jaiswal, Haznita Abd Karim, Bei Chao Zhang, Johnny Cham, Ravi Sankar Yelamanchi, Chee Kong Leong
-
Publication number: 20020191668Abstract: A method for controlling and/or calibrating rapid thermal process systems is described. One or more wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon are silicided in a RTP system at different temperatures. Sheet resistance uniformity of the wafer is measured thereby detecting silicidation phase transition temperature points at the highest uniformity points. The temperature points are used to calibrate or to reset the RTP system. A plurality of wafers comprising a silicon semiconductor substrate having a refractory metal layer thereon can be silicided in each of a plurality of rapid thermal process systems. Sheet resistance uniformity of each of the wafers is measured thereby detecting silicidation phase transition temperature points by highest sheet resistance uniformity for each of the RTP systems. The temperature points are used to match temperatures for each of the RTP systems.Type: ApplicationFiled: May 31, 2001Publication date: December 19, 2002Inventors: Zhong-Yun Zhu, Rajneesh Jaiswal, Haznita Abd Karim, Bei Chao Zhang, Johnny Cham, Ravi Sankar Yelamanchi, Chee Kong Leong