Abstract: A digital signal processor includes a parallel multiplier having first and second input ports, in which the first input port has conductors for many more bits than does the second input port. First and second data selectors are connected respectively to the first and second ports to enable data from a RAM and data from a ROM to be selectively applied to either or both ports, directly or via a pipe-line register. The second data selector can select two or more groups of bits from the RAM or ROM to enable the multiplier to multiply numbers having more bits than can be input at the second input port at one time. A third data selector is connected to the output port of the multiplier and is capable of shifting the product received relative to the output conductors to effect multiplication by powers of two. A particular application of the processor is for processing pulse coded speech signals.